ACE: a digital floating point CNN emulator engine
The architecture of ACE, a multiprocessor analogic cellular neural network (CNN) emulator engine consisting of 2 to 16 TMS320C40 floating point DSPs is introduced. The engine containing up to 512 Mbyte RAM (enough to store a 512/spl times/512/spl times/512 sized CNN cube) which can be controlled thr...
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| creator | Feher, B. Szolgay, P. Roska, T. Radvanyi, A.G. Sziranyi, T. Csapodi, M. Laszlo, K. Nemes, L. Szatmari, I. Toth, G. Venetianer, P.L. |
| description | The architecture of ACE, a multiprocessor analogic cellular neural network (CNN) emulator engine consisting of 2 to 16 TMS320C40 floating point DSPs is introduced. The engine containing up to 512 Mbyte RAM (enough to store a 512/spl times/512/spl times/512 sized CNN cube) which can be controlled through its SCSI port. It can either accelerate the multilayer CNN simulator CNNM or be accessed directly from the high level, C-based analogic CNN language ACL to achieve the simulation speed of /spl sim/2.8 /spl mu/sec/cell/iteration/DSP for 3/spl times/3 linear templates. |
| doi_str_mv | 10.1109/CNNA.1996.566574 |
| format | Conference Proceeding |
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| identifier | ISBN: 9780780332614 |
| ispartof | 1996 Fourth IEEE International Workshop on Cellular Neural Networks and their Applications Proceedings (CNNA-96), 1996, p.273-278 |
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| language | eng |
| recordid | cdi_ieee_primary_566574 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Cellular neural networks Computational modeling Computer architecture Digital signal processing Engines Hardware Logic arrays Programmable logic arrays Signal processing algorithms Very large scale integration |
| title | ACE: a digital floating point CNN emulator engine |
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