Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis

Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. However, when deciding to adopt this emerging tec...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yibo Chen, Dimin Niu, Yuan Xie, Chakrabarty, K
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Integrated circuit modeling Solid modeling Stacking Testing Three dimensional displays Through-silicon vias
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