Design and implementation of low power digital phase-locked loop

This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed arc...

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Hauptverfasser:	Saber, M, Jitsumatsu, Y, Khan, M T A
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Detectors Digital filters Digital phase lock loop(DPLL) field programmable gate array (FPGA) Frequency control look-up table (LUT) numerically controlled oscillator (NCO) Phase locked loops Power demand software defined radio (SDR) spurious free dynamic range (SFDR) Table lookup
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creator	Saber, M Jitsumatsu, Y Khan, M T A
description	This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock frequency which means a more than 25% saving in power consumption compared to traditional NCO. Furthermore, proposed method also saves FPGA resources and works at faster clock frequency.
doi_str_mv	10.1109/ISITA.2010.5649551
format	Conference Proceeding
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High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock frequency which means a more than 25% saving in power consumption compared to traditional NCO. Furthermore, proposed method also saves FPGA resources and works at faster clock frequency.</description><subject>Clocks</subject><subject>Detectors</subject><subject>Digital filters</subject><subject>Digital phase lock loop(DPLL)</subject><subject>field programmable gate array (FPGA)</subject><subject>Frequency control</subject><subject>look-up table (LUT)</subject><subject>numerically controlled oscillator (NCO)</subject><subject>Phase locked loops</subject><subject>Power demand</subject><subject>software defined radio (SDR)</subject><subject>spurious free dynamic range (SFDR)</subject><subject>Table lookup</subject><isbn>9781424460168</isbn><isbn>1424460166</isbn><isbn>9781424460175</isbn><isbn>1424460174</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVT01LxDAUjIigrP0Deskf6PpemqTNzWX9Kix4sPflbfq6RtumtIXFf2_BvTiHGYYZBkaIO4Q1IriH8qOsNmsFizdWO2PwQiQuL1ArrS1gbi7_eVtci2SavmCBUXkGeCMen3gKx15SX8vQDS133M80h9jL2Mg2nuQQTzzKOhzDTK0cPmnitI3-m-sljsOtuGqonTg560pUL8_V9i3dvb-W280uDQ7m1CAftF2IvGsAGG3jVO6t0o6MslTUCKDZ1sRLCag4OOcVeARi3bgsW4n7v9nAzPthDB2NP_vz7ewXheNLWg</recordid><startdate>201010</startdate><enddate>201010</enddate><creator>Saber, M</creator><creator>Jitsumatsu, Y</creator><creator>Khan, M T A</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201010</creationdate><title>Design and implementation of low power digital phase-locked loop</title><author>Saber, M ; Jitsumatsu, Y ; Khan, M T A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-51eb461ebac9f00e16f927c6249a526a8d1004e6dae1eb0a8b99c20c10ae4f933</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Clocks</topic><topic>Detectors</topic><topic>Digital filters</topic><topic>Digital phase lock loop(DPLL)</topic><topic>field programmable gate array (FPGA)</topic><topic>Frequency control</topic><topic>look-up table (LUT)</topic><topic>numerically controlled oscillator (NCO)</topic><topic>Phase locked loops</topic><topic>Power demand</topic><topic>software defined radio (SDR)</topic><topic>spurious free dynamic range (SFDR)</topic><topic>Table lookup</topic><toplevel>online_resources</toplevel><creatorcontrib>Saber, M</creatorcontrib><creatorcontrib>Jitsumatsu, Y</creatorcontrib><creatorcontrib>Khan, M T A</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Saber, M</au><au>Jitsumatsu, Y</au><au>Khan, M T A</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design and implementation of low power digital phase-locked loop</atitle><btitle>2010 International Symposium On Information Theory & Its Applications</btitle><stitle>ISITA</stitle><date>2010-10</date><risdate>2010</risdate><spage>928</spage><epage>933</epage><pages>928-933</pages><isbn>9781424460168</isbn><isbn>1424460166</isbn><eisbn>9781424460175</eisbn><eisbn>1424460174</eisbn><abstract>This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock frequency which means a more than 25% saving in power consumption compared to traditional NCO. Furthermore, proposed method also saves FPGA resources and works at faster clock frequency.</abstract><pub>IEEE</pub><doi>10.1109/ISITA.2010.5649551</doi><tpages>6</tpages></addata></record>
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identifier	ISBN: 9781424460168
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language	eng
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Clocks Detectors Digital filters Digital phase lock loop(DPLL) field programmable gate array (FPGA) Frequency control look-up table (LUT) numerically controlled oscillator (NCO) Phase locked loops Power demand software defined radio (SDR) spurious free dynamic range (SFDR) Table lookup
title	Design and implementation of low power digital phase-locked loop
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