An all digital frequency-locked loop immune to hysteresis effects for power management of multicore processors

Low power design has always been critical to high performance. With the latest technologies, being able to significantly reduce any portion of the overall system power becomes an absolute requirement for extending the lifetime of the system. Clock generation and clock tree distribution are always id...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Tretz, C, Chen Guo, Jacobowitz, L
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automatic frequency control Clocks Hysteresis Jacobian matrices Monitoring Multicore processing Table lookup
Online-Zugang:	Volltext bestellen
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