A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip

3D IC process has be a tendency in recent years. But the progress of IC process technologies recently has the related problems. In the 3D NoC architecture, the 3D IC process makes the placement and routing to become more complex. Then, the faults increase because of the more complex architecture. Th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Min-Ju Chan, Chun-Lung Hsu
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Built-in self-test built-in self-test (BIST) Circuit faults Integrated circuit interconnections interconnect testing network-on-chip (NoC) Three dimensional displays Wires
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!