Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG

In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method is targeted to systems on chip (SoCs)provided with the P1500 test standard. The RESPIN architecture can be used for test patt...

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Bibliographische Detailangaben

Hauptverfasser:	Balcárek, Jiří, Fišer, Petr, Schmidt, J
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	ATPG Benchmark testing Circuit faults Compression algorithms SAT System-on-a-chip Test pattern generators Test patterns compression testing
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