Chip-package co-design for mixed SoC
A chip-package co-design method is presented for high frequency mixed SoC. Based on the analysis of simulation result of package and chip, a RC circuit which is composed of resistor and capacitor is designed on chip to suppress the affect of Simultaneous Switch Noise(SSN). Consequently, chip-package...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 351 |
|---|---|
| container_issue | |
| container_start_page | 349 |
| container_title | |
| container_volume | |
| creator | Yuhan Gao Lintao Liu Liang Chen Ruzhang Li Ruimin Xu |
| description | A chip-package co-design method is presented for high frequency mixed SoC. Based on the analysis of simulation result of package and chip, a RC circuit which is composed of resistor and capacitor is designed on chip to suppress the affect of Simultaneous Switch Noise(SSN). Consequently, chip-package co-simulation achieves a good agreement with measurement as the co-design method is used to predict the performance of mixed SoC. |
| doi_str_mv | 10.1109/RCSLPLT.2010.5615311 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5615311</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5615311</ieee_id><sourcerecordid>5615311</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-d2df83321608c1cd23246b261cf39f6010dd7a5439decd87fda14a0fe35c10303</originalsourceid><addsrcrecordid>eNo1j8tOwzAURI1QJWjJF8AiC7Yu914_Yi-RxUuKBKLZV8aPYqAkSljA3xOJMpvRzGJ0hrELhDUi2Ktnt2mf2m5NMDdKoxKIR6yyjUFJUiqFpI_Z8j8gLtiSAKxFEApPWDVNbzBLKiJjT9mley0DH3x497tUh57HNJXdZ537sd6X7xTrTe_O2CL7jylVB1-x7vamc_e8fbx7cNctLxa-eKSYjRCEGkzAEEmQ1C-kMWRhs56BY2y8ksLGFKJpcvQoPeQkVJjpQKzY-d9sSSlth7Hs_fizPZwUv97oQZo</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Chip-package co-design for mixed SoC</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Yuhan Gao ; Lintao Liu ; Liang Chen ; Ruzhang Li ; Ruimin Xu</creator><creatorcontrib>Yuhan Gao ; Lintao Liu ; Liang Chen ; Ruzhang Li ; Ruimin Xu</creatorcontrib><description>A chip-package co-design method is presented for high frequency mixed SoC. Based on the analysis of simulation result of package and chip, a RC circuit which is composed of resistor and capacitor is designed on chip to suppress the affect of Simultaneous Switch Noise(SSN). Consequently, chip-package co-simulation achieves a good agreement with measurement as the co-design method is used to predict the performance of mixed SoC.</description><identifier>ISBN: 1424455111</identifier><identifier>ISBN: 9781424455119</identifier><identifier>EISBN: 9781424455126</identifier><identifier>EISBN: 142445512X</identifier><identifier>EISBN: 1424455138</identifier><identifier>EISBN: 9781424455133</identifier><identifier>DOI: 10.1109/RCSLPLT.2010.5615311</identifier><identifier>LCCN: 2009910351</identifier><language>eng</language><publisher>IEEE</publisher><subject>chip-package ; co-design ; Equivalent circuits ; Integrated circuit modeling ; Noise ; RC circuit ; Semiconductor device measurement ; Simulation ; SoC ; SSN ; System-on-a-chip ; Wire</subject><ispartof>2010 Academic Symposium on Optoelectronics and Microelectronics Technology and 10th Chinese-Russian Symposium on Laser Physics and Laser TechnologyOptoelectronics Technology (ASOT), 2010, p.349-351</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5615311$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5615311$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yuhan Gao</creatorcontrib><creatorcontrib>Lintao Liu</creatorcontrib><creatorcontrib>Liang Chen</creatorcontrib><creatorcontrib>Ruzhang Li</creatorcontrib><creatorcontrib>Ruimin Xu</creatorcontrib><title>Chip-package co-design for mixed SoC</title><title>2010 Academic Symposium on Optoelectronics and Microelectronics Technology and 10th Chinese-Russian Symposium on Laser Physics and Laser TechnologyOptoelectronics Technology (ASOT)</title><addtitle>RCSLPLT</addtitle><description>A chip-package co-design method is presented for high frequency mixed SoC. Based on the analysis of simulation result of package and chip, a RC circuit which is composed of resistor and capacitor is designed on chip to suppress the affect of Simultaneous Switch Noise(SSN). Consequently, chip-package co-simulation achieves a good agreement with measurement as the co-design method is used to predict the performance of mixed SoC.</description><subject>chip-package</subject><subject>co-design</subject><subject>Equivalent circuits</subject><subject>Integrated circuit modeling</subject><subject>Noise</subject><subject>RC circuit</subject><subject>Semiconductor device measurement</subject><subject>Simulation</subject><subject>SoC</subject><subject>SSN</subject><subject>System-on-a-chip</subject><subject>Wire</subject><isbn>1424455111</isbn><isbn>9781424455119</isbn><isbn>9781424455126</isbn><isbn>142445512X</isbn><isbn>1424455138</isbn><isbn>9781424455133</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j8tOwzAURI1QJWjJF8AiC7Yu914_Yi-RxUuKBKLZV8aPYqAkSljA3xOJMpvRzGJ0hrELhDUi2Ktnt2mf2m5NMDdKoxKIR6yyjUFJUiqFpI_Z8j8gLtiSAKxFEApPWDVNbzBLKiJjT9mley0DH3x497tUh57HNJXdZ537sd6X7xTrTe_O2CL7jylVB1-x7vamc_e8fbx7cNctLxa-eKSYjRCEGkzAEEmQ1C-kMWRhs56BY2y8ksLGFKJpcvQoPeQkVJjpQKzY-d9sSSlth7Hs_fizPZwUv97oQZo</recordid><startdate>201007</startdate><enddate>201007</enddate><creator>Yuhan Gao</creator><creator>Lintao Liu</creator><creator>Liang Chen</creator><creator>Ruzhang Li</creator><creator>Ruimin Xu</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201007</creationdate><title>Chip-package co-design for mixed SoC</title><author>Yuhan Gao ; Lintao Liu ; Liang Chen ; Ruzhang Li ; Ruimin Xu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-d2df83321608c1cd23246b261cf39f6010dd7a5439decd87fda14a0fe35c10303</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>chip-package</topic><topic>co-design</topic><topic>Equivalent circuits</topic><topic>Integrated circuit modeling</topic><topic>Noise</topic><topic>RC circuit</topic><topic>Semiconductor device measurement</topic><topic>Simulation</topic><topic>SoC</topic><topic>SSN</topic><topic>System-on-a-chip</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Yuhan Gao</creatorcontrib><creatorcontrib>Lintao Liu</creatorcontrib><creatorcontrib>Liang Chen</creatorcontrib><creatorcontrib>Ruzhang Li</creatorcontrib><creatorcontrib>Ruimin Xu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yuhan Gao</au><au>Lintao Liu</au><au>Liang Chen</au><au>Ruzhang Li</au><au>Ruimin Xu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Chip-package co-design for mixed SoC</atitle><btitle>2010 Academic Symposium on Optoelectronics and Microelectronics Technology and 10th Chinese-Russian Symposium on Laser Physics and Laser TechnologyOptoelectronics Technology (ASOT)</btitle><stitle>RCSLPLT</stitle><date>2010-07</date><risdate>2010</risdate><spage>349</spage><epage>351</epage><pages>349-351</pages><isbn>1424455111</isbn><isbn>9781424455119</isbn><eisbn>9781424455126</eisbn><eisbn>142445512X</eisbn><eisbn>1424455138</eisbn><eisbn>9781424455133</eisbn><abstract>A chip-package co-design method is presented for high frequency mixed SoC. Based on the analysis of simulation result of package and chip, a RC circuit which is composed of resistor and capacitor is designed on chip to suppress the affect of Simultaneous Switch Noise(SSN). Consequently, chip-package co-simulation achieves a good agreement with measurement as the co-design method is used to predict the performance of mixed SoC.</abstract><pub>IEEE</pub><doi>10.1109/RCSLPLT.2010.5615311</doi><tpages>3</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 1424455111 |
| ispartof | 2010 Academic Symposium on Optoelectronics and Microelectronics Technology and 10th Chinese-Russian Symposium on Laser Physics and Laser TechnologyOptoelectronics Technology (ASOT), 2010, p.349-351 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_5615311 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | chip-package co-design Equivalent circuits Integrated circuit modeling Noise RC circuit Semiconductor device measurement Simulation SoC SSN System-on-a-chip Wire |
| title | Chip-package co-design for mixed SoC |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T07%3A22%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Chip-package%20co-design%20for%20mixed%20SoC&rft.btitle=2010%20Academic%20Symposium%20on%20Optoelectronics%20and%20Microelectronics%20Technology%20and%2010th%20Chinese-Russian%20Symposium%20on%20Laser%20Physics%20and%20Laser%20TechnologyOptoelectronics%20Technology%20(ASOT)&rft.au=Yuhan%20Gao&rft.date=2010-07&rft.spage=349&rft.epage=351&rft.pages=349-351&rft.isbn=1424455111&rft.isbn_list=9781424455119&rft_id=info:doi/10.1109/RCSLPLT.2010.5615311&rft_dat=%3Cieee_6IE%3E5615311%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424455126&rft.eisbn_list=142445512X&rft.eisbn_list=1424455138&rft.eisbn_list=9781424455133&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5615311&rfr_iscdi=true |