Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their ma...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Seong-Dong Kim, Jain, Sameer, Rhee, Hwasung, Scholze, Andreas, Yu, Mickey, Seung Chul Lee, Furkay, Stephen, Zorzi, Marco, Bufler, Fabian M, Erlebach, Axel
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Contact resistance Logic gates Performance evaluation Resistance Semiconductor process modeling Silicides Stress
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