Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their ma...

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Hauptverfasser:	Seong-Dong Kim, Jain, Sameer, Rhee, Hwasung, Scholze, Andreas, Yu, Mickey, Seung Chul Lee, Furkay, Stephen, Zorzi, Marco, Bufler, Fabian M, Erlebach, Axel
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Contact resistance Logic gates Performance evaluation Resistance Semiconductor process modeling Silicides Stress
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creator	Seong-Dong Kim Jain, Sameer Rhee, Hwasung Scholze, Andreas Yu, Mickey Seung Chul Lee Furkay, Stephen Zorzi, Marco Bufler, Fabian M Erlebach, Axel
description	The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using R on -L gate measurements of 32nm-node devices with different gate-pitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch.
doi_str_mv	10.1109/SISPAD.2010.5604566
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5604566</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5604566</ieee_id><sourcerecordid>5604566</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-13e86ebc8db28f0d9ade2998297c5bc2253e1f5e08009d30bc758e814c3f0a223</originalsourceid><addsrcrecordid>eNpFkMtKAzEYheMNrLVP0E1eYOqfzGSSLEu9FVoqVMFdyST_1GgnUyYR7Ns7aNHVge8cvsUhZMxgwhjom_V8_TS9nXDogSihEGV5Qq5YwYtCSoDXUzJguigzJqQ8-y-YOv8rSn1JRjG-AwDjquRSDcjHsnW482FLtyZhtvfJvtFozQ_yzd7YRNtAY-owxswH92nR0aat_M6nAzXBUfxK2AWzo_3Ex2SCRVq3HeUQmiz0erpcre_vnuM1uajNLuLomEPy0uPZY7ZYPcxn00XmmRQpYzmqEiurXMVVDU4bh1xrxbW0orKcixxZLRAUgHY5VFYKhYoVNq_BcJ4PyfjX6xFxs-98Y7rD5nha_g2ruF2S</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Seong-Dong Kim ; Jain, Sameer ; Rhee, Hwasung ; Scholze, Andreas ; Yu, Mickey ; Seung Chul Lee ; Furkay, Stephen ; Zorzi, Marco ; Bufler, Fabian M ; Erlebach, Axel</creator><creatorcontrib>Seong-Dong Kim ; Jain, Sameer ; Rhee, Hwasung ; Scholze, Andreas ; Yu, Mickey ; Seung Chul Lee ; Furkay, Stephen ; Zorzi, Marco ; Bufler, Fabian M ; Erlebach, Axel</creatorcontrib><description>The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using R on -L gate measurements of 32nm-node devices with different gate-pitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch.</description><identifier>ISSN: 1946-1569</identifier><identifier>ISBN: 1424477018</identifier><identifier>ISBN: 9781424477012</identifier><identifier>EISSN: 1946-1577</identifier><identifier>EISBN: 142447700X</identifier><identifier>EISBN: 9781424477005</identifier><identifier>DOI: 10.1109/SISPAD.2010.5604566</identifier><language>eng</language><publisher>IEEE</publisher><subject>Contact resistance ; Logic gates ; Performance evaluation ; Resistance ; Semiconductor process modeling ; Silicides ; Stress</subject><ispartof>2010 International Conference on Simulation of Semiconductor Processes and Devices, 2010, p.79-82</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5604566$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5604566$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Seong-Dong Kim</creatorcontrib><creatorcontrib>Jain, Sameer</creatorcontrib><creatorcontrib>Rhee, Hwasung</creatorcontrib><creatorcontrib>Scholze, Andreas</creatorcontrib><creatorcontrib>Yu, Mickey</creatorcontrib><creatorcontrib>Seung Chul Lee</creatorcontrib><creatorcontrib>Furkay, Stephen</creatorcontrib><creatorcontrib>Zorzi, Marco</creatorcontrib><creatorcontrib>Bufler, Fabian M</creatorcontrib><creatorcontrib>Erlebach, Axel</creatorcontrib><title>Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs</title><title>2010 International Conference on Simulation of Semiconductor Processes and Devices</title><addtitle>SISPAD</addtitle><description>The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using R on -L gate measurements of 32nm-node devices with different gate-pitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch.</description><subject>Contact resistance</subject><subject>Logic gates</subject><subject>Performance evaluation</subject><subject>Resistance</subject><subject>Semiconductor process modeling</subject><subject>Silicides</subject><subject>Stress</subject><issn>1946-1569</issn><issn>1946-1577</issn><isbn>1424477018</isbn><isbn>9781424477012</isbn><isbn>142447700X</isbn><isbn>9781424477005</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkMtKAzEYheMNrLVP0E1eYOqfzGSSLEu9FVoqVMFdyST_1GgnUyYR7Ns7aNHVge8cvsUhZMxgwhjom_V8_TS9nXDogSihEGV5Qq5YwYtCSoDXUzJguigzJqQ8-y-YOv8rSn1JRjG-AwDjquRSDcjHsnW482FLtyZhtvfJvtFozQ_yzd7YRNtAY-owxswH92nR0aat_M6nAzXBUfxK2AWzo_3Ex2SCRVq3HeUQmiz0erpcre_vnuM1uajNLuLomEPy0uPZY7ZYPcxn00XmmRQpYzmqEiurXMVVDU4bh1xrxbW0orKcixxZLRAUgHY5VFYKhYoVNq_BcJ4PyfjX6xFxs-98Y7rD5nha_g2ruF2S</recordid><startdate>201009</startdate><enddate>201009</enddate><creator>Seong-Dong Kim</creator><creator>Jain, Sameer</creator><creator>Rhee, Hwasung</creator><creator>Scholze, Andreas</creator><creator>Yu, Mickey</creator><creator>Seung Chul Lee</creator><creator>Furkay, Stephen</creator><creator>Zorzi, Marco</creator><creator>Bufler, Fabian M</creator><creator>Erlebach, Axel</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201009</creationdate><title>Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs</title><author>Seong-Dong Kim ; Jain, Sameer ; Rhee, Hwasung ; Scholze, Andreas ; Yu, Mickey ; Seung Chul Lee ; Furkay, Stephen ; Zorzi, Marco ; Bufler, Fabian M ; Erlebach, Axel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-13e86ebc8db28f0d9ade2998297c5bc2253e1f5e08009d30bc758e814c3f0a223</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Contact resistance</topic><topic>Logic gates</topic><topic>Performance evaluation</topic><topic>Resistance</topic><topic>Semiconductor process modeling</topic><topic>Silicides</topic><topic>Stress</topic><toplevel>online_resources</toplevel><creatorcontrib>Seong-Dong Kim</creatorcontrib><creatorcontrib>Jain, Sameer</creatorcontrib><creatorcontrib>Rhee, Hwasung</creatorcontrib><creatorcontrib>Scholze, Andreas</creatorcontrib><creatorcontrib>Yu, Mickey</creatorcontrib><creatorcontrib>Seung Chul Lee</creatorcontrib><creatorcontrib>Furkay, Stephen</creatorcontrib><creatorcontrib>Zorzi, Marco</creatorcontrib><creatorcontrib>Bufler, Fabian M</creatorcontrib><creatorcontrib>Erlebach, Axel</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Seong-Dong Kim</au><au>Jain, Sameer</au><au>Rhee, Hwasung</au><au>Scholze, Andreas</au><au>Yu, Mickey</au><au>Seung Chul Lee</au><au>Furkay, Stephen</au><au>Zorzi, Marco</au><au>Bufler, Fabian M</au><au>Erlebach, Axel</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs</atitle><btitle>2010 International Conference on Simulation of Semiconductor Processes and Devices</btitle><stitle>SISPAD</stitle><date>2010-09</date><risdate>2010</risdate><spage>79</spage><epage>82</epage><pages>79-82</pages><issn>1946-1569</issn><eissn>1946-1577</eissn><isbn>1424477018</isbn><isbn>9781424477012</isbn><eisbn>142447700X</eisbn><eisbn>9781424477005</eisbn><abstract>The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using R on -L gate measurements of 32nm-node devices with different gate-pitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch.</abstract><pub>IEEE</pub><doi>10.1109/SISPAD.2010.5604566</doi><tpages>4</tpages></addata></record>
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subjects	Contact resistance Logic gates Performance evaluation Resistance Semiconductor process modeling Silicides Stress
title	Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-20T19%3A49%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Modeling%20gate-pitch%20scaling%20impact%20on%20stress-induced%20mobility%20and%20external%20resistance%20for%2020nm-node%20MOSFETs&rft.btitle=2010%20International%20Conference%20on%20Simulation%20of%20Semiconductor%20Processes%20and%20Devices&rft.au=Seong-Dong%20Kim&rft.date=2010-09&rft.spage=79&rft.epage=82&rft.pages=79-82&rft.issn=1946-1569&rft.eissn=1946-1577&rft.isbn=1424477018&rft.isbn_list=9781424477012&rft_id=info:doi/10.1109/SISPAD.2010.5604566&rft_dat=%3Cieee_6IE%3E5604566%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=142447700X&rft.eisbn_list=9781424477005&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5604566&rfr_iscdi=true