A comparison of pipelined parallel and iterative CORDIC design on FPGA

Many hardware efficient algorithms exists for hardware signal processing architecture. Among these algorithm is a set of shift-add algorithms collectively known as CORDIC (Coordinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic,...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bhakthavatchalu, Ramesh, Sinith, M S, Nair, Parvathi, Jismi, K
Format:	Tagungsbericht
Sprache:	eng ; jpn
Schlagworte:	Algorithm design and analysis Clocks Computer architecture Field programmable gate arrays Hardware Iterative CORDIC Mathematical model Parallel CORDIC Pipelined CORDIC Signal processing algorithms Vector rotation Vector translation
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