A comparison of pipelined parallel and iterative CORDIC design on FPGA
Many hardware efficient algorithms exists for hardware signal processing architecture. Among these algorithm is a set of shift-add algorithms collectively known as CORDIC (Coordinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic,...
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| creator | Bhakthavatchalu, Ramesh Sinith, M S Nair, Parvathi Jismi, K |
| description | Many hardware efficient algorithms exists for hardware signal processing architecture. Among these algorithm is a set of shift-add algorithms collectively known as CORDIC (Coordinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. The paper compares the different CORDIC architectures with respect to their area, speed, and data throughput performance especially in three different major styles iterative, parallel and pipelined structures. All three designs were designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools. |
| doi_str_mv | 10.1109/ICIINFS.2010.5578702 |
| format | Conference Proceeding |
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| ispartof | 2010 5th International Conference on Industrial and Information Systems, 2010, p.239-243 |
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| language | eng ; jpn |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Clocks Computer architecture Field programmable gate arrays Hardware Iterative CORDIC Mathematical model Parallel CORDIC Pipelined CORDIC Signal processing algorithms Vector rotation Vector translation |
| title | A comparison of pipelined parallel and iterative CORDIC design on FPGA |
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