Retimed two-step CRC computation on FPGA
Previously, a two-step approach to perform the cyclic redundancy check (CRC) computation in hardware was presented. In that approach, an architecture is constructed from a suitable multiple polynomial for a fixed generator polynomial and input size. In this paper, we revisit the two-step approach an...
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Format: | Tagungsbericht |
Sprache: | eng |
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Zusammenfassung: | Previously, a two-step approach to perform the cyclic redundancy check (CRC) computation in hardware was presented. In that approach, an architecture is constructed from a suitable multiple polynomial for a fixed generator polynomial and input size. In this paper, we revisit the two-step approach and suggest a modification to its architecture. First, we propose retiming the second step to the delay of the first step in order to obtain a parallel CRC computation architecture with minimal critical path delay. Next, we propose a software algorithm to find multiple polynomials and identify ones for some useful cases. Finally, implementations are carried out on a Xil-inx Virtex-5 field-programmable gate array (FPGA) device, comparing the proposed architecture with the original. As expected, the proposed architecture demonstrates improvements in timing at the cost of additional area. |
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ISSN: | 0840-7789 2576-7046 |
DOI: | 10.1109/CCECE.2010.5575253 |