Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach
The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dy...
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| creator | Candaele, B Aguirre, S Sarlotte, M Anagnostopoulos, I Xydis, S Bartzas, A Bekiaris, D Soudris, D Zhonghai Lu Xiaowen Chen Chabloz, J Hemani, A Jantsch, A Vanmeerbeeck, G Kreku, J Tiensyrja, K Ieromnimon, F Kritharidis, D Wiefrink, A Vanthournout, B Martin, P |
| description | The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. |
| doi_str_mv | 10.1109/ISVLSI.2010.71 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>swepub_6IE</sourceid><recordid>TN_cdi_ieee_primary_5572841</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5572841</ieee_id><sourcerecordid>oai_DiVA_org_kth_63629</sourcerecordid><originalsourceid>FETCH-LOGICAL-i212t-934724dfa70524d743daf4d07a681fab58ea9214bd4e5be87574157030460a083</originalsourceid><addsrcrecordid>eNo9jktPwkAUhcdXIiBbN27mB1icZ6fjrgEfJCAJrWyb23ZKRwttpiXGf28Nyuok9_vuyUHolpIJpUQ_zKPNIppPGOkPip6hsVYBFUwIxRmR52jAqNQeF0pdoOE_oOryBHx9jYZt-0EI_30coLclNI3db_Gq6ezOttDZeo-L2uEogwrSyuDloeqsl9XO4HCdlTY2WXdw5hHHZQ9XUbiOcdg0roasvEFXBVStGf_lCL0_P8XTV2-xeplPw4VnGWWdp_uJTOQFKCL7VILnUIicKPADWkAqAwOaUZHmwsjUBEoqQaUinAifAAn4CN0fe9sv0xzSpHF2B-47qcEmM7sJk9ptk8-uTHzuM93rd0fdGmNOspSKBYLyH6KdYDw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Candaele, B ; Aguirre, S ; Sarlotte, M ; Anagnostopoulos, I ; Xydis, S ; Bartzas, A ; Bekiaris, D ; Soudris, D ; Zhonghai Lu ; Xiaowen Chen ; Chabloz, J ; Hemani, A ; Jantsch, A ; Vanmeerbeeck, G ; Kreku, J ; Tiensyrja, K ; Ieromnimon, F ; Kritharidis, D ; Wiefrink, A ; Vanthournout, B ; Martin, P</creator><creatorcontrib>Candaele, B ; Aguirre, S ; Sarlotte, M ; Anagnostopoulos, I ; Xydis, S ; Bartzas, A ; Bekiaris, D ; Soudris, D ; Zhonghai Lu ; Xiaowen Chen ; Chabloz, J ; Hemani, A ; Jantsch, A ; Vanmeerbeeck, G ; Kreku, J ; Tiensyrja, K ; Ieromnimon, F ; Kritharidis, D ; Wiefrink, A ; Vanthournout, B ; Martin, P</creatorcontrib><description>The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.</description><identifier>ISSN: 2159-3469</identifier><identifier>ISBN: 1424473217</identifier><identifier>ISBN: 9781424473212</identifier><identifier>ISBN: 9780769540764</identifier><identifier>ISBN: 0769540767</identifier><identifier>EISSN: 2159-3477</identifier><identifier>EISBN: 9781424473205</identifier><identifier>EISBN: 9780769540764</identifier><identifier>EISBN: 1424473209</identifier><identifier>EISBN: 0769540767</identifier><identifier>DOI: 10.1109/ISVLSI.2010.71</identifier><language>eng</language><publisher>IEEE</publisher><subject>ASIP exploration ; Computational modeling ; Data structures ; Distributed databases ; Load modeling ; Memory architecture ; Memory management ; memory services ; Middleware ; Network on Chip ; Parallelization ; System-level exploration ; VLSI circuits ; Wireless communication</subject><ispartof>2010 IEEE Computer Society Annual Symposium on VLSI, 2010, p.518-523</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5572841$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,881,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5572841$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-63629$$DView record from Swedish Publication Index$$Hfree_for_read</backlink></links><search><creatorcontrib>Candaele, B</creatorcontrib><creatorcontrib>Aguirre, S</creatorcontrib><creatorcontrib>Sarlotte, M</creatorcontrib><creatorcontrib>Anagnostopoulos, I</creatorcontrib><creatorcontrib>Xydis, S</creatorcontrib><creatorcontrib>Bartzas, A</creatorcontrib><creatorcontrib>Bekiaris, D</creatorcontrib><creatorcontrib>Soudris, D</creatorcontrib><creatorcontrib>Zhonghai Lu</creatorcontrib><creatorcontrib>Xiaowen Chen</creatorcontrib><creatorcontrib>Chabloz, J</creatorcontrib><creatorcontrib>Hemani, A</creatorcontrib><creatorcontrib>Jantsch, A</creatorcontrib><creatorcontrib>Vanmeerbeeck, G</creatorcontrib><creatorcontrib>Kreku, J</creatorcontrib><creatorcontrib>Tiensyrja, K</creatorcontrib><creatorcontrib>Ieromnimon, F</creatorcontrib><creatorcontrib>Kritharidis, D</creatorcontrib><creatorcontrib>Wiefrink, A</creatorcontrib><creatorcontrib>Vanthournout, B</creatorcontrib><creatorcontrib>Martin, P</creatorcontrib><title>Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach</title><title>2010 IEEE Computer Society Annual Symposium on VLSI</title><addtitle>ISVLSI</addtitle><description>The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.</description><subject>ASIP exploration</subject><subject>Computational modeling</subject><subject>Data structures</subject><subject>Distributed databases</subject><subject>Load modeling</subject><subject>Memory architecture</subject><subject>Memory management</subject><subject>memory services</subject><subject>Middleware</subject><subject>Network on Chip</subject><subject>Parallelization</subject><subject>System-level exploration</subject><subject>VLSI circuits</subject><subject>Wireless communication</subject><issn>2159-3469</issn><issn>2159-3477</issn><isbn>1424473217</isbn><isbn>9781424473212</isbn><isbn>9780769540764</isbn><isbn>0769540767</isbn><isbn>9781424473205</isbn><isbn>9780769540764</isbn><isbn>1424473209</isbn><isbn>0769540767</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9jktPwkAUhcdXIiBbN27mB1icZ6fjrgEfJCAJrWyb23ZKRwttpiXGf28Nyuok9_vuyUHolpIJpUQ_zKPNIppPGOkPip6hsVYBFUwIxRmR52jAqNQeF0pdoOE_oOryBHx9jYZt-0EI_30coLclNI3db_Gq6ezOttDZeo-L2uEogwrSyuDloeqsl9XO4HCdlTY2WXdw5hHHZQ9XUbiOcdg0roasvEFXBVStGf_lCL0_P8XTV2-xeplPw4VnGWWdp_uJTOQFKCL7VILnUIicKPADWkAqAwOaUZHmwsjUBEoqQaUinAifAAn4CN0fe9sv0xzSpHF2B-47qcEmM7sJk9ptk8-uTHzuM93rd0fdGmNOspSKBYLyH6KdYDw</recordid><startdate>201007</startdate><enddate>201007</enddate><creator>Candaele, B</creator><creator>Aguirre, S</creator><creator>Sarlotte, M</creator><creator>Anagnostopoulos, I</creator><creator>Xydis, S</creator><creator>Bartzas, A</creator><creator>Bekiaris, D</creator><creator>Soudris, D</creator><creator>Zhonghai Lu</creator><creator>Xiaowen Chen</creator><creator>Chabloz, J</creator><creator>Hemani, A</creator><creator>Jantsch, A</creator><creator>Vanmeerbeeck, G</creator><creator>Kreku, J</creator><creator>Tiensyrja, K</creator><creator>Ieromnimon, F</creator><creator>Kritharidis, D</creator><creator>Wiefrink, A</creator><creator>Vanthournout, B</creator><creator>Martin, P</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>ADTPV</scope><scope>BNKNJ</scope><scope>D8V</scope></search><sort><creationdate>201007</creationdate><title>Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach</title><author>Candaele, B ; Aguirre, S ; Sarlotte, M ; Anagnostopoulos, I ; Xydis, S ; Bartzas, A ; Bekiaris, D ; Soudris, D ; Zhonghai Lu ; Xiaowen Chen ; Chabloz, J ; Hemani, A ; Jantsch, A ; Vanmeerbeeck, G ; Kreku, J ; Tiensyrja, K ; Ieromnimon, F ; Kritharidis, D ; Wiefrink, A ; Vanthournout, B ; Martin, P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i212t-934724dfa70524d743daf4d07a681fab58ea9214bd4e5be87574157030460a083</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>ASIP exploration</topic><topic>Computational modeling</topic><topic>Data structures</topic><topic>Distributed databases</topic><topic>Load modeling</topic><topic>Memory architecture</topic><topic>Memory management</topic><topic>memory services</topic><topic>Middleware</topic><topic>Network on Chip</topic><topic>Parallelization</topic><topic>System-level exploration</topic><topic>VLSI circuits</topic><topic>Wireless communication</topic><toplevel>online_resources</toplevel><creatorcontrib>Candaele, B</creatorcontrib><creatorcontrib>Aguirre, S</creatorcontrib><creatorcontrib>Sarlotte, M</creatorcontrib><creatorcontrib>Anagnostopoulos, I</creatorcontrib><creatorcontrib>Xydis, S</creatorcontrib><creatorcontrib>Bartzas, A</creatorcontrib><creatorcontrib>Bekiaris, D</creatorcontrib><creatorcontrib>Soudris, D</creatorcontrib><creatorcontrib>Zhonghai Lu</creatorcontrib><creatorcontrib>Xiaowen Chen</creatorcontrib><creatorcontrib>Chabloz, J</creatorcontrib><creatorcontrib>Hemani, A</creatorcontrib><creatorcontrib>Jantsch, A</creatorcontrib><creatorcontrib>Vanmeerbeeck, G</creatorcontrib><creatorcontrib>Kreku, J</creatorcontrib><creatorcontrib>Tiensyrja, K</creatorcontrib><creatorcontrib>Ieromnimon, F</creatorcontrib><creatorcontrib>Kritharidis, D</creatorcontrib><creatorcontrib>Wiefrink, A</creatorcontrib><creatorcontrib>Vanthournout, B</creatorcontrib><creatorcontrib>Martin, P</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>SwePub</collection><collection>SwePub Conference</collection><collection>SWEPUB Kungliga Tekniska Högskolan</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Candaele, B</au><au>Aguirre, S</au><au>Sarlotte, M</au><au>Anagnostopoulos, I</au><au>Xydis, S</au><au>Bartzas, A</au><au>Bekiaris, D</au><au>Soudris, D</au><au>Zhonghai Lu</au><au>Xiaowen Chen</au><au>Chabloz, J</au><au>Hemani, A</au><au>Jantsch, A</au><au>Vanmeerbeeck, G</au><au>Kreku, J</au><au>Tiensyrja, K</au><au>Ieromnimon, F</au><au>Kritharidis, D</au><au>Wiefrink, A</au><au>Vanthournout, B</au><au>Martin, P</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach</atitle><btitle>2010 IEEE Computer Society Annual Symposium on VLSI</btitle><stitle>ISVLSI</stitle><date>2010-07</date><risdate>2010</risdate><spage>518</spage><epage>523</epage><pages>518-523</pages><issn>2159-3469</issn><eissn>2159-3477</eissn><isbn>1424473217</isbn><isbn>9781424473212</isbn><isbn>9780769540764</isbn><isbn>0769540767</isbn><eisbn>9781424473205</eisbn><eisbn>9780769540764</eisbn><eisbn>1424473209</eisbn><eisbn>0769540767</eisbn><abstract>The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.</abstract><pub>IEEE</pub><doi>10.1109/ISVLSI.2010.71</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2159-3469 |
| ispartof | 2010 IEEE Computer Society Annual Symposium on VLSI, 2010, p.518-523 |
| issn | 2159-3469 2159-3477 |
| language | eng |
| recordid | cdi_ieee_primary_5572841 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | ASIP exploration Computational modeling Data structures Distributed databases Load modeling Memory architecture Memory management memory services Middleware Network on Chip Parallelization System-level exploration VLSI circuits Wireless communication |
| title | Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T13%3A35%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-swepub_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Mapping%20Optimisation%20for%20Scalable%20Multi-core%20ARchiTecture:%20The%20MOSART%20Approach&rft.btitle=2010%20IEEE%20Computer%20Society%20Annual%20Symposium%20on%20VLSI&rft.au=Candaele,%20B&rft.date=2010-07&rft.spage=518&rft.epage=523&rft.pages=518-523&rft.issn=2159-3469&rft.eissn=2159-3477&rft.isbn=1424473217&rft.isbn_list=9781424473212&rft.isbn_list=9780769540764&rft.isbn_list=0769540767&rft_id=info:doi/10.1109/ISVLSI.2010.71&rft_dat=%3Cswepub_6IE%3Eoai_DiVA_org_kth_63629%3C/swepub_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424473205&rft.eisbn_list=9780769540764&rft.eisbn_list=1424473209&rft.eisbn_list=0769540767&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5572841&rfr_iscdi=true |