Mixed-mode BIST using embedded processors
In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random...
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| creator | Hellebrand, S. Wunderlich, H.-J. Hertwig, A. |
| description | In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements. In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware. |
| doi_str_mv | 10.1109/TEST.1996.556962 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_556962</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>556962</ieee_id><sourcerecordid>556962</sourcerecordid><originalsourceid>FETCH-LOGICAL-i172t-f4a6734990fc28ff952415914f4e83cbc76d1a7a87881f7626d532b93d3abcd13</originalsourceid><addsrcrecordid>eNotj01LAzEUAIMfYK29i6e9esia916-3lFL1ULFQ9dzyW4SWXHdslHQf69QYWBuAyPEJagaQPFNs9o2NTDb2hjLFo_EDMl5iWjUsViw8-oPIqPBnYgZKM-SDPGZOC_lTSlUBtVMXD_13ynKYYypultvm-qr9B-vVRraFGOK1X4au1TKOJULcZrDe0mLf8_Fy_2qWT7KzfPDenm7kT04_JRZB-tIM6vcoc-ZDWowDDrr5KlrO2cjBBe88x6ys2ijIWyZIoW2i0BzcXXo9iml3X7qhzD97A6T9AuRIUHN</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Mixed-mode BIST using embedded processors</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Hellebrand, S. ; Wunderlich, H.-J. ; Hertwig, A.</creator><creatorcontrib>Hellebrand, S. ; Wunderlich, H.-J. ; Hertwig, A.</creatorcontrib><description>In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements. In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.</description><identifier>ISSN: 1089-3539</identifier><identifier>ISBN: 9780780335417</identifier><identifier>ISBN: 0780335414</identifier><identifier>EISSN: 2378-2250</identifier><identifier>DOI: 10.1109/TEST.1996.556962</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application specific integrated circuits ; Built-in self-test ; Costs ; Embedded computing ; Embedded software ; Hardware ; Polynomials ; Software testing ; System testing ; Test pattern generators</subject><ispartof>Proceedings International Test Conference 1996. Test and Design Validity, 1996, p.195-204</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/556962$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/556962$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hellebrand, S.</creatorcontrib><creatorcontrib>Wunderlich, H.-J.</creatorcontrib><creatorcontrib>Hertwig, A.</creatorcontrib><title>Mixed-mode BIST using embedded processors</title><title>Proceedings International Test Conference 1996. Test and Design Validity</title><addtitle>TEST</addtitle><description>In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements. In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.</description><subject>Application specific integrated circuits</subject><subject>Built-in self-test</subject><subject>Costs</subject><subject>Embedded computing</subject><subject>Embedded software</subject><subject>Hardware</subject><subject>Polynomials</subject><subject>Software testing</subject><subject>System testing</subject><subject>Test pattern generators</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>9780780335417</isbn><isbn>0780335414</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj01LAzEUAIMfYK29i6e9esia916-3lFL1ULFQ9dzyW4SWXHdslHQf69QYWBuAyPEJagaQPFNs9o2NTDb2hjLFo_EDMl5iWjUsViw8-oPIqPBnYgZKM-SDPGZOC_lTSlUBtVMXD_13ynKYYypultvm-qr9B-vVRraFGOK1X4au1TKOJULcZrDe0mLf8_Fy_2qWT7KzfPDenm7kT04_JRZB-tIM6vcoc-ZDWowDDrr5KlrO2cjBBe88x6ys2ijIWyZIoW2i0BzcXXo9iml3X7qhzD97A6T9AuRIUHN</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Hellebrand, S.</creator><creator>Wunderlich, H.-J.</creator><creator>Hertwig, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1996</creationdate><title>Mixed-mode BIST using embedded processors</title><author>Hellebrand, S. ; Wunderlich, H.-J. ; Hertwig, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-f4a6734990fc28ff952415914f4e83cbc76d1a7a87881f7626d532b93d3abcd13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Application specific integrated circuits</topic><topic>Built-in self-test</topic><topic>Costs</topic><topic>Embedded computing</topic><topic>Embedded software</topic><topic>Hardware</topic><topic>Polynomials</topic><topic>Software testing</topic><topic>System testing</topic><topic>Test pattern generators</topic><toplevel>online_resources</toplevel><creatorcontrib>Hellebrand, S.</creatorcontrib><creatorcontrib>Wunderlich, H.-J.</creatorcontrib><creatorcontrib>Hertwig, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hellebrand, S.</au><au>Wunderlich, H.-J.</au><au>Hertwig, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Mixed-mode BIST using embedded processors</atitle><btitle>Proceedings International Test Conference 1996. Test and Design Validity</btitle><stitle>TEST</stitle><date>1996</date><risdate>1996</risdate><spage>195</spage><epage>204</epage><pages>195-204</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>9780780335417</isbn><isbn>0780335414</isbn><abstract>In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements. In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.</abstract><pub>IEEE</pub><doi>10.1109/TEST.1996.556962</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 1089-3539 |
| ispartof | Proceedings International Test Conference 1996. Test and Design Validity, 1996, p.195-204 |
| issn | 1089-3539 2378-2250 |
| language | eng |
| recordid | cdi_ieee_primary_556962 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application specific integrated circuits Built-in self-test Costs Embedded computing Embedded software Hardware Polynomials Software testing System testing Test pattern generators |
| title | Mixed-mode BIST using embedded processors |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T19%3A07%3A34IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Mixed-mode%20BIST%20using%20embedded%20processors&rft.btitle=Proceedings%20International%20Test%20Conference%201996.%20Test%20and%20Design%20Validity&rft.au=Hellebrand,%20S.&rft.date=1996&rft.spage=195&rft.epage=204&rft.pages=195-204&rft.issn=1089-3539&rft.eissn=2378-2250&rft.isbn=9780780335417&rft.isbn_list=0780335414&rft_id=info:doi/10.1109/TEST.1996.556962&rft_dat=%3Cieee_6IE%3E556962%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=556962&rfr_iscdi=true |