Design-technology interaction for post-32 nm node CMOS technologies

Design-technology interaction for post-32 nm node CMOS technologies

This paper will review the technology features in the recent and upcoming nodes and how they will impact circuit design, product performance, and migratability. It will cover the challenges and serious limitations that we will face in FEOL (increased leakage, loss of body effect), BEOL (RC, electro-...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Shahidi, G G
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Cooling
Immune system
Lithography
Logic gates
Materials
Metallization
Performance evaluation
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 144
container_issue
container_start_page 143
container_title
container_volume
creator Shahidi, G G
description This paper will review the technology features in the recent and upcoming nodes and how they will impact circuit design, product performance, and migratability. It will cover the challenges and serious limitations that we will face in FEOL (increased leakage, loss of body effect), BEOL (RC, electro-migration), lithography (ever more complex design rules), and power management (end of frequency scaling, very high device count). We will talk about some possible technology solutions that will address some of the above challenges (disruptive device technologies, increased number of BEOL levels, and migration to lower voltages). Net is that scaling is expected to continue to 11 nm (at least). Design is expected to become significantly more complex.
doi_str_mv 10.1109/VLSIT.2010.5556204
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5556204</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5556204</ieee_id><sourcerecordid>5556204</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-7fb35bb55615d33dd5daa58ffea02b85f4c11332eed3600651122c18c3e30db43</originalsourceid><addsrcrecordid>eNo9kM1OwkAUhccoiYC8gG7mBQbvnTu3P0tTRUkwLEC3pO3c4hhoSdsNb28T0dXJl3w5OTlK3SPMESF9_Fxtltu5hYGZObLgrtQEnXWOHUN0rWZpnPwxJjdqDLEjg4M6UuMUTMSMhLdq0nXfABaYkrHKnqUL-9r0Un7VzaHZn3Woe2nzsg9Nraum1aem6w1ZXR913XjR2ft6o__9IN2dGlX5oZPZJafqY_Gyzd7Mav26zJ5WJmDMvYmrgrgohu3Insh79nnOSVVJDrZIuHIlIpEV8RQBRIxobYlJSULgC0dT9fDbG0Rkd2rDMW_Pu8sZ9AOLyU5c</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Design-technology interaction for post-32 nm node CMOS technologies</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Shahidi, G G</creator><creatorcontrib>Shahidi, G G</creatorcontrib><description>This paper will review the technology features in the recent and upcoming nodes and how they will impact circuit design, product performance, and migratability. It will cover the challenges and serious limitations that we will face in FEOL (increased leakage, loss of body effect), BEOL (RC, electro-migration), lithography (ever more complex design rules), and power management (end of frequency scaling, very high device count). We will talk about some possible technology solutions that will address some of the above challenges (disruptive device technologies, increased number of BEOL levels, and migration to lower voltages). Net is that scaling is expected to continue to 11 nm (at least). Design is expected to become significantly more complex.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 9781424454518</identifier><identifier>ISBN: 1424454514</identifier><identifier>EISBN: 1424454506</identifier><identifier>EISBN: 9781424454501</identifier><identifier>DOI: 10.1109/VLSIT.2010.5556204</identifier><identifier>LCCN: 90-655131</identifier><language>eng</language><publisher>IEEE</publisher><subject>Cooling ; Immune system ; Lithography ; Logic gates ; Materials ; Metallization ; Performance evaluation</subject><ispartof>2010 Symposium on VLSI Technology, 2010, p.143-144</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5556204$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5556204$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Shahidi, G G</creatorcontrib><title>Design-technology interaction for post-32 nm node CMOS technologies</title><title>2010 Symposium on VLSI Technology</title><addtitle>VLSIT</addtitle><description>This paper will review the technology features in the recent and upcoming nodes and how they will impact circuit design, product performance, and migratability. It will cover the challenges and serious limitations that we will face in FEOL (increased leakage, loss of body effect), BEOL (RC, electro-migration), lithography (ever more complex design rules), and power management (end of frequency scaling, very high device count). We will talk about some possible technology solutions that will address some of the above challenges (disruptive device technologies, increased number of BEOL levels, and migration to lower voltages). Net is that scaling is expected to continue to 11 nm (at least). Design is expected to become significantly more complex.</description><subject>Cooling</subject><subject>Immune system</subject><subject>Lithography</subject><subject>Logic gates</subject><subject>Materials</subject><subject>Metallization</subject><subject>Performance evaluation</subject><issn>0743-1562</issn><isbn>9781424454518</isbn><isbn>1424454514</isbn><isbn>1424454506</isbn><isbn>9781424454501</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kM1OwkAUhccoiYC8gG7mBQbvnTu3P0tTRUkwLEC3pO3c4hhoSdsNb28T0dXJl3w5OTlK3SPMESF9_Fxtltu5hYGZObLgrtQEnXWOHUN0rWZpnPwxJjdqDLEjg4M6UuMUTMSMhLdq0nXfABaYkrHKnqUL-9r0Un7VzaHZn3Woe2nzsg9Nraum1aem6w1ZXR913XjR2ft6o__9IN2dGlX5oZPZJafqY_Gyzd7Mav26zJ5WJmDMvYmrgrgohu3Insh79nnOSVVJDrZIuHIlIpEV8RQBRIxobYlJSULgC0dT9fDbG0Rkd2rDMW_Pu8sZ9AOLyU5c</recordid><startdate>201006</startdate><enddate>201006</enddate><creator>Shahidi, G G</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201006</creationdate><title>Design-technology interaction for post-32 nm node CMOS technologies</title><author>Shahidi, G G</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-7fb35bb55615d33dd5daa58ffea02b85f4c11332eed3600651122c18c3e30db43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Cooling</topic><topic>Immune system</topic><topic>Lithography</topic><topic>Logic gates</topic><topic>Materials</topic><topic>Metallization</topic><topic>Performance evaluation</topic><toplevel>online_resources</toplevel><creatorcontrib>Shahidi, G G</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shahidi, G G</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design-technology interaction for post-32 nm node CMOS technologies</atitle><btitle>2010 Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2010-06</date><risdate>2010</risdate><spage>143</spage><epage>144</epage><pages>143-144</pages><issn>0743-1562</issn><isbn>9781424454518</isbn><isbn>1424454514</isbn><eisbn>1424454506</eisbn><eisbn>9781424454501</eisbn><abstract>This paper will review the technology features in the recent and upcoming nodes and how they will impact circuit design, product performance, and migratability. It will cover the challenges and serious limitations that we will face in FEOL (increased leakage, loss of body effect), BEOL (RC, electro-migration), lithography (ever more complex design rules), and power management (end of frequency scaling, very high device count). We will talk about some possible technology solutions that will address some of the above challenges (disruptive device technologies, increased number of BEOL levels, and migration to lower voltages). Net is that scaling is expected to continue to 11 nm (at least). Design is expected to become significantly more complex.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2010.5556204</doi><tpages>2</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0743-1562
ispartof 2010 Symposium on VLSI Technology, 2010, p.143-144
issn 0743-1562
language eng
recordid cdi_ieee_primary_5556204
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Cooling
Immune system
Lithography
Logic gates
Materials
Metallization
Performance evaluation
title Design-technology interaction for post-32 nm node CMOS technologies
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T21%3A54%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Design-technology%20interaction%20for%20post-32%20nm%20node%20CMOS%20technologies&rft.btitle=2010%20Symposium%20on%20VLSI%20Technology&rft.au=Shahidi,%20G%20G&rft.date=2010-06&rft.spage=143&rft.epage=144&rft.pages=143-144&rft.issn=0743-1562&rft.isbn=9781424454518&rft.isbn_list=1424454514&rft_id=info:doi/10.1109/VLSIT.2010.5556204&rft_dat=%3Cieee_6IE%3E5556204%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424454506&rft.eisbn_list=9781424454501&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5556204&rfr_iscdi=true