TSPC-DICE: A single phase clock high performance SEU hardened flip-flop

This paper presents a true single-phase clock (TSPC) flip-flop that is robust against radiation-induced single event upsets (SEUs) or soft errors. The flip-flop consists of an input stage that uses a single phase clock to pass the data to a storage unit at the positive edge of the clock. The single...

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Bibliographische Detailangaben

Hauptverfasser:	Jahinuzzaman, S M, Islam, R
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits Clocks CMOS technology Cosmic radiation fault tolerance flip-flop Flip-flops Latches Logic Microprocessors Neutrons Robustness Single event upset
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