Logic-compatible embedded DRAM design for memory intensive low power systems

Circuit techniques for enabling a low power logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes preferential storage node boosting to improve data retention time and increase read margin. A regulated bit-line write scheme is equipped with a steady-state storage node...

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Hauptverfasser:	Ki Chul Chun, Jain, P, Kim, C H
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Boosting Circuits Monitoring Power measurement Power systems Random access memory Semiconductor device measurement Steady-state Time measurement Voltage
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creator	Ki Chul Chun Jain, P Kim, C H
description	Circuit techniques for enabling a low power logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes preferential storage node boosting to improve data retention time and increase read margin. A regulated bit-line write scheme is equipped with a steady-state storage node voltage monitor to overcome the data `1' write disturbance problem. An adaptive and die-to-die adjustable read reference bias generator is proposed to cope with PVT variations. Measurement data from 65nm test chips demonstrate a >1.0msec retention time at 0.9V, 85°C and a
doi_str_mv	10.1109/ISCAS.2010.5537877
format	Conference Proceeding
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subjects	Boosting Circuits Monitoring Power measurement Power systems Random access memory Semiconductor device measurement Steady-state Time measurement Voltage
title	Logic-compatible embedded DRAM design for memory intensive low power systems
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