Hierarchical data structure-based timing controller design for plasma display panels

In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels (PDPs). Also, we used a double buffering and a repeatable FIFO in order to reduce the workload of memory accesses for control data, and provided a graphical user interfac...

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Hauptverfasser:	Yeoul Na, Seok Joong Hwang, Giseong Bak, Seon Wook Kim, Cheol Ho Lee, Junkyu Min, Taejin Kim
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Brightness Control systems Flash memory Plasma displays Prototypes Signal design Signal generators Switches Timing Voltage
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creator	Yeoul Na Seok Joong Hwang Giseong Bak Seon Wook Kim Cheol Ho Lee Junkyu Min Taejin Kim
description	In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels (PDPs). Also, we used a double buffering and a repeatable FIFO in order to reduce the workload of memory accesses for control data, and provided a graphical user interface program for easy control data management. Our prototype system runs at 83 MHz on Spartan-3A DSP FPGA, and the new design achieves the reduction of 73 % in resource usage from the previous implementation.
doi_str_mv	10.1109/ISCAS.2010.5537616
format	Conference Proceeding
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subjects	Brightness Control systems Flash memory Plasma displays Prototypes Signal design Signal generators Switches Timing Voltage
title	Hierarchical data structure-based timing controller design for plasma display panels
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