A Ku-band down-converter with perfect differential PLL in 0.18um CMOS
This paper presents a Ku-band down converter that includes perfect differential PLL in a 0.18 μm CMOS technology. This front-end down-converts the input signal from the Ku-band (10.5~13 GHz) to the IF (~2.3 GHz). This fully integrated down-converter is dedicated to both satellite receivers and micro...
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| creator | Miyashita, K |
| description | This paper presents a Ku-band down converter that includes perfect differential PLL in a 0.18 μm CMOS technology. This front-end down-converts the input signal from the Ku-band (10.5~13 GHz) to the IF (~2.3 GHz). This fully integrated down-converter is dedicated to both satellite receivers and microwave link products. The perfect differential PLL shows very low supply voltage sensitivity (Kpss=-0.18[%/V]), making it possible to eliminate on chip regulator. A novel model-matched layout design methodology not only enhance ft but also reduce risk of non-convergences. The down converter performance include 5.5 dB gain; 4.35 dBm IIP3; -107 dBc/Hz phase noise at 1 MHz offset; 0.41 psec jitter; and current consumption is 102 mA from a 1.8 V supply. |
| doi_str_mv | 10.1109/ISCAS.2010.5537556 |
| format | Conference Proceeding |
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This front-end down-converts the input signal from the Ku-band (10.5~13 GHz) to the IF (~2.3 GHz). This fully integrated down-converter is dedicated to both satellite receivers and microwave link products. The perfect differential PLL shows very low supply voltage sensitivity (Kpss=-0.18[%/V]), making it possible to eliminate on chip regulator. A novel model-matched layout design methodology not only enhance ft but also reduce risk of non-convergences. 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This front-end down-converts the input signal from the Ku-band (10.5~13 GHz) to the IF (~2.3 GHz). This fully integrated down-converter is dedicated to both satellite receivers and microwave link products. The perfect differential PLL shows very low supply voltage sensitivity (Kpss=-0.18[%/V]), making it possible to eliminate on chip regulator. A novel model-matched layout design methodology not only enhance ft but also reduce risk of non-convergences. The down converter performance include 5.5 dB gain; 4.35 dBm IIP3; -107 dBc/Hz phase noise at 1 MHz offset; 0.41 psec jitter; and current consumption is 102 mA from a 1.8 V supply.</description><subject>CMOS integrated circuits</subject><subject>CMOS process</subject><subject>Phase frequency detector</subject><subject>Phase locked loops</subject><subject>Phase noise</subject><subject>Power supplies</subject><subject>Radio frequency</subject><subject>Satellite broadcasting</subject><subject>Semiconductor device modeling</subject><subject>Voltage-controlled oscillators</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424453089</isbn><isbn>9781424453085</isbn><isbn>9781424453092</isbn><isbn>1424453097</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1UNtKw0AUXC8FY-0P6Mv-wNazl7PZfSyhajFSoX0va_YEV9q0JKnFvzdgnZdhGBhmhrF7CVMpwT8uVsVsNVUwaESdI9oLNvG5k0YZgxq8umSZkuiERIVX7PbfcP6aZaByKYwGNWKZA2GNHZwbNum6LxhgUFmdZ2w-469H8RGayOP-1Ihq33xT21PLT6n_5Adqa6p6HlNdU0tNn8KWv5clTw0farrjjhdvy9UdG9Vh29HkzGO2fpqvixdRLp8XxawUyUMvgtS2ksZFrxW6qMgNHXX0lYwB8ioYjeQVBlDOO5RSGkJCC7YOEIeheswe_mITEW0ObdqF9mdzPkf_Aoz9ToA</recordid><startdate>201005</startdate><enddate>201005</enddate><creator>Miyashita, K</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201005</creationdate><title>A Ku-band down-converter with perfect differential PLL in 0.18um CMOS</title><author>Miyashita, K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-a136c148d93258d2e82713d9c1da07ca435e925a0289851114e5e5606fa0d2153</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>CMOS integrated circuits</topic><topic>CMOS process</topic><topic>Phase frequency detector</topic><topic>Phase locked loops</topic><topic>Phase noise</topic><topic>Power supplies</topic><topic>Radio frequency</topic><topic>Satellite broadcasting</topic><topic>Semiconductor device modeling</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Miyashita, K</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Miyashita, K</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Ku-band down-converter with perfect differential PLL in 0.18um CMOS</atitle><btitle>2010 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2010-05</date><risdate>2010</risdate><spage>4289</spage><epage>4292</epage><pages>4289-4292</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424453089</isbn><isbn>9781424453085</isbn><eisbn>9781424453092</eisbn><eisbn>1424453097</eisbn><abstract>This paper presents a Ku-band down converter that includes perfect differential PLL in a 0.18 μm CMOS technology. This front-end down-converts the input signal from the Ku-band (10.5~13 GHz) to the IF (~2.3 GHz). This fully integrated down-converter is dedicated to both satellite receivers and microwave link products. The perfect differential PLL shows very low supply voltage sensitivity (Kpss=-0.18[%/V]), making it possible to eliminate on chip regulator. A novel model-matched layout design methodology not only enhance ft but also reduce risk of non-convergences. The down converter performance include 5.5 dB gain; 4.35 dBm IIP3; -107 dBc/Hz phase noise at 1 MHz offset; 0.41 psec jitter; and current consumption is 102 mA from a 1.8 V supply.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2010.5537556</doi><tpages>4</tpages></addata></record> |
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| ispartof | 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.4289-4292 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_5537556 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS integrated circuits CMOS process Phase frequency detector Phase locked loops Phase noise Power supplies Radio frequency Satellite broadcasting Semiconductor device modeling Voltage-controlled oscillators |
| title | A Ku-band down-converter with perfect differential PLL in 0.18um CMOS |
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