Power gating for ultra-low voltage nanometer ICs

A novel power gating (PG) structure using series-connected low-V th power switches has been developed to extend the PG structure to the ultra-low voltage region while keeping low leakage power in sleep mode. The series-connected low-V th power switches induce a short wake-up time due to fast current...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kyung Ki Kim, Haiqing Nan, Ken Choi
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit simulation CMOS technology Delay effects Inverters Leakage current Size control Switches Switching circuits Tunneling Voltage
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