Two-step junction-splitting SAR analog-to-digital converter

A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analog-to-digital converters (SAR ADCs). Two junction-split binary-weighted capacitor arrays are used in a coarse/fine quantization scheme. This reduces both the power consumption a...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Wenhuan Yu, Jiaming Lin, Temes, G C
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analog-digital conversion Capacitors Circuits Energy consumption Phased arrays Quantization Sampling methods Signal resolution Switches Voltage
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