Two-step junction-splitting SAR analog-to-digital converter

A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analog-to-digital converters (SAR ADCs). Two junction-split binary-weighted capacitor arrays are used in a coarse/fine quantization scheme. This reduces both the power consumption a...

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Hauptverfasser:	Wenhuan Yu, Jiaming Lin, Temes, G C
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analog-digital conversion Capacitors Circuits Energy consumption Phased arrays Quantization Sampling methods Signal resolution Switches Voltage
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creator	Wenhuan Yu Jiaming Lin Temes, G C
description	A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analog-to-digital converters (SAR ADCs). Two junction-split binary-weighted capacitor arrays are used in a coarse/fine quantization scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC.
doi_str_mv	10.1109/ISCAS.2010.5537325
format	Conference Proceeding
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Analog-digital conversion Capacitors Circuits Energy consumption Phased arrays Quantization Sampling methods Signal resolution Switches Voltage
title	Two-step junction-splitting SAR analog-to-digital converter
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