Networks-on-chip topology optimization subject to power, delay, and reliability constraints

In this paper, we present a novel approach in Networks-on-Chip topology optimization, by considering the network power consumption, packet transmission delay, and system reliability, simultaneously. We use the Particle Swarm Optimization technique to acquire the most suitable topology architecture, which achieves maximum reliability as well as minimum delay and power consumption. The optimization problem, which considers six design variables: network topology architecture, traffic distribution, processing elements' mapping, noise power, voltage swing, and probability of edge failure, is validated through a case study of an H.263-encoder MP3-decoder.