Combining circuit and packet switching with bus architecture in a NoC for real-time applications
Real-Time applications generate both streaming and best-effort traffics. The on-chip interconnection network for these applications must be able to guarantee Quality of Service "QoS" for streaming traffic and no packet loss for best-effort traffic. In order to efficiently handle both strea...
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| creator | Lusala, A K Legat, J |
| description | Real-Time applications generate both streaming and best-effort traffics. The on-chip interconnection network for these applications must be able to guarantee Quality of Service "QoS" for streaming traffic and no packet loss for best-effort traffic. In order to efficiently handle both streaming and best-effort traffic, we propose in this paper a hybrid network on chip architecture, which combines CDMA-based circuit switching, packet switching and CDMA-based bus. We show that with the proposed architecture, bounds on latency and throughput can be configurable according to application constraints, thereby meeting QoS requirements in a hybrid traffic environment. |
| doi_str_mv | 10.1109/ISCAS.2010.5536964 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5536964</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5536964</ieee_id><sourcerecordid>5536964</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-bdd6d058e6fa055640069e2f3ed66f2acf31d031d00317b83f7a249ff892f2023</originalsourceid><addsrcrecordid>eNo1kMtOwzAQRc2jEqH0B2DjH3AZP2Mvq4hHpQoWhXVxHJsa2iRyXCH-niDKSHfunTnSLAahawpzSsHcLtfVYj1nMM5ScmWUOEEzU2oqmBCSg2GnqGBUakIlk2fo8h9oc44KYCUlggOboEIDUUKN5ALNhuEDxhKSKV4W6K3q9nVsY_uOXUzuEDO2bYN76z59xsNXzG77C8ewxfVhwDaNi-xdPiSPY4stfuoqHLqEk7c7kuPeY9v3u-hsjl07XKFJsLvBz44-Ra_3dy_VI1k9PyyrxYpEWspM6qZRDUjtVbAgpRIAyngWuG-UCsy6wGkDvxpbWWseSsuECUEbFhgwPkU3f3ej937Tp7i36XtzfBz_Ae5CW68</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Combining circuit and packet switching with bus architecture in a NoC for real-time applications</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Lusala, A K ; Legat, J</creator><creatorcontrib>Lusala, A K ; Legat, J</creatorcontrib><description>Real-Time applications generate both streaming and best-effort traffics. The on-chip interconnection network for these applications must be able to guarantee Quality of Service "QoS" for streaming traffic and no packet loss for best-effort traffic. In order to efficiently handle both streaming and best-effort traffic, we propose in this paper a hybrid network on chip architecture, which combines CDMA-based circuit switching, packet switching and CDMA-based bus. We show that with the proposed architecture, bounds on latency and throughput can be configurable according to application constraints, thereby meeting QoS requirements in a hybrid traffic environment.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 1424453089</identifier><identifier>ISBN: 9781424453085</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 9781424453092</identifier><identifier>EISBN: 1424453097</identifier><identifier>DOI: 10.1109/ISCAS.2010.5536964</identifier><identifier>LCCN: 80-646530</identifier><language>eng</language><publisher>IEEE</publisher><subject>Communication switching ; Integrated circuit interconnections ; Multiaccess communication ; Network-on-a-chip ; Packet switching ; Quality of service ; Switching circuits ; System-on-a-chip ; Telecommunication traffic ; Traffic control</subject><ispartof>2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.2880-2883</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5536964$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5536964$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lusala, A K</creatorcontrib><creatorcontrib>Legat, J</creatorcontrib><title>Combining circuit and packet switching with bus architecture in a NoC for real-time applications</title><title>2010 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>Real-Time applications generate both streaming and best-effort traffics. The on-chip interconnection network for these applications must be able to guarantee Quality of Service "QoS" for streaming traffic and no packet loss for best-effort traffic. In order to efficiently handle both streaming and best-effort traffic, we propose in this paper a hybrid network on chip architecture, which combines CDMA-based circuit switching, packet switching and CDMA-based bus. We show that with the proposed architecture, bounds on latency and throughput can be configurable according to application constraints, thereby meeting QoS requirements in a hybrid traffic environment.</description><subject>Communication switching</subject><subject>Integrated circuit interconnections</subject><subject>Multiaccess communication</subject><subject>Network-on-a-chip</subject><subject>Packet switching</subject><subject>Quality of service</subject><subject>Switching circuits</subject><subject>System-on-a-chip</subject><subject>Telecommunication traffic</subject><subject>Traffic control</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424453089</isbn><isbn>9781424453085</isbn><isbn>9781424453092</isbn><isbn>1424453097</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kMtOwzAQRc2jEqH0B2DjH3AZP2Mvq4hHpQoWhXVxHJsa2iRyXCH-niDKSHfunTnSLAahawpzSsHcLtfVYj1nMM5ScmWUOEEzU2oqmBCSg2GnqGBUakIlk2fo8h9oc44KYCUlggOboEIDUUKN5ALNhuEDxhKSKV4W6K3q9nVsY_uOXUzuEDO2bYN76z59xsNXzG77C8ewxfVhwDaNi-xdPiSPY4stfuoqHLqEk7c7kuPeY9v3u-hsjl07XKFJsLvBz44-Ra_3dy_VI1k9PyyrxYpEWspM6qZRDUjtVbAgpRIAyngWuG-UCsy6wGkDvxpbWWseSsuECUEbFhgwPkU3f3ej937Tp7i36XtzfBz_Ae5CW68</recordid><startdate>201005</startdate><enddate>201005</enddate><creator>Lusala, A K</creator><creator>Legat, J</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201005</creationdate><title>Combining circuit and packet switching with bus architecture in a NoC for real-time applications</title><author>Lusala, A K ; Legat, J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-bdd6d058e6fa055640069e2f3ed66f2acf31d031d00317b83f7a249ff892f2023</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Communication switching</topic><topic>Integrated circuit interconnections</topic><topic>Multiaccess communication</topic><topic>Network-on-a-chip</topic><topic>Packet switching</topic><topic>Quality of service</topic><topic>Switching circuits</topic><topic>System-on-a-chip</topic><topic>Telecommunication traffic</topic><topic>Traffic control</topic><toplevel>online_resources</toplevel><creatorcontrib>Lusala, A K</creatorcontrib><creatorcontrib>Legat, J</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lusala, A K</au><au>Legat, J</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Combining circuit and packet switching with bus architecture in a NoC for real-time applications</atitle><btitle>2010 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2010-05</date><risdate>2010</risdate><spage>2880</spage><epage>2883</epage><pages>2880-2883</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424453089</isbn><isbn>9781424453085</isbn><eisbn>9781424453092</eisbn><eisbn>1424453097</eisbn><abstract>Real-Time applications generate both streaming and best-effort traffics. The on-chip interconnection network for these applications must be able to guarantee Quality of Service "QoS" for streaming traffic and no packet loss for best-effort traffic. In order to efficiently handle both streaming and best-effort traffic, we propose in this paper a hybrid network on chip architecture, which combines CDMA-based circuit switching, packet switching and CDMA-based bus. We show that with the proposed architecture, bounds on latency and throughput can be configurable according to application constraints, thereby meeting QoS requirements in a hybrid traffic environment.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2010.5536964</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 0271-4302 |
| ispartof | 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.2880-2883 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_5536964 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Communication switching Integrated circuit interconnections Multiaccess communication Network-on-a-chip Packet switching Quality of service Switching circuits System-on-a-chip Telecommunication traffic Traffic control |
| title | Combining circuit and packet switching with bus architecture in a NoC for real-time applications |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T00%3A41%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Combining%20circuit%20and%20packet%20switching%20with%20bus%20architecture%20in%20a%20NoC%20for%20real-time%20applications&rft.btitle=2010%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Lusala,%20A%20K&rft.date=2010-05&rft.spage=2880&rft.epage=2883&rft.pages=2880-2883&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=1424453089&rft.isbn_list=9781424453085&rft_id=info:doi/10.1109/ISCAS.2010.5536964&rft_dat=%3Cieee_6IE%3E5536964%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424453092&rft.eisbn_list=1424453097&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5536964&rfr_iscdi=true |