TSV stress aware timing analysis with applications to 3D-IC layout optimization

As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different temperature...

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Bibliographische Detailangaben
Hauptverfasser:	Yang, Jae-Seok, Athikulwongse, Krit, Lee, Young-Joon, Lim, Sung Kyu, Pan, David Z.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	3DIC Delay Geometry Hardware > Electronic design automation > Physical design (EDA) mobility variation Silicon Stacking stress Tensile stress Thermal expansion Thermal stresses Three-dimensional integrated circuits Through-silicon vias Timing timing analysis TSV
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