SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy

Embedded systems designers are free to choose the most suitable configuration of L1 cache in modern processor based SoCs. Choosing the appropriate L1 cache configuration necessitates the simulation of long memory access traces to accurately obtain hit/miss rates. The long execution time taken to sim...

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Bibliographische Detailangaben
Hauptverfasser:	Haque, Mohammad Shihabul, Peddersen, Jorgen, Janapsatya, Andhi, Parameswaran, Sri
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analytical models Australia Cache memory Cache simulation Data structures Embedded system Energy consumption General and reference > Cross-computing tools and techniques > Performance Hardware > Hardware validation L1 cache Miss rate Performance analysis Permission Process design Round robin Simulation
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