A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction
Flash memories are based on the floating gate technology allowing the write and erase data electronically. Such a technology can be prone to complex defects leading to faulty behaviors. In this paper, we introduce an electrical model of the ATMEL TSTACTM eFlash memory technology. The model is compos...
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| creator | Mauroux, P.-D Virazel, A Bosio, A Dilillo, L Girard, P Pravossoudovitch, S Godard, B Festes, G Vachez, L |
| description | Flash memories are based on the floating gate technology allowing the write and erase data electronically. Such a technology can be prone to complex defects leading to faulty behaviors. In this paper, we introduce an electrical model of the ATMEL TSTACTM eFlash memory technology. The model is composed of two layers: a functional layer representing the floating gate and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model has been validated by means of simulations and comparisons with ATMEL silicon data. We apply this model for the analysis of defect-induced failures. As a case study, a resistive defect injection is considered. |
| doi_str_mv | 10.1109/ETSYM.2010.5512776 |
| format | Conference Proceeding |
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As a case study, a resistive defect injection is considered.</description><subject>coupling effects</subject><subject>defects</subject><subject>Dynamic programming</subject><subject>electrical model</subject><subject>embedded Flash</subject><subject>fault modeling</subject><subject>Flash memory</subject><subject>Fowler-Nordheim</subject><subject>Functional programming</subject><subject>Logic programming</subject><subject>Nonvolatile memory</subject><subject>Predictive models</subject><subject>Silicon</subject><subject>SPICE</subject><subject>Testing</subject><subject>Voltage</subject><issn>1530-1877</issn><issn>1558-1780</issn><isbn>142445834X</isbn><isbn>9781424458349</isbn><isbn>1424458358</isbn><isbn>9781424458332</isbn><isbn>1424458331</isbn><isbn>9781424458325</isbn><isbn>1424458323</isbn><isbn>9781424458356</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkEtOwzAURc1PopRuACbeQIq_tTOMohYqtQKpGcCocuJnkiqJqySAwpiVsDRWQoBKvMnV1Tm6g4fQFSVTSkl4M082T-spI0OXkjKlZkfoggomhNRc6mM0olLqgCpNTv6BeDz9AZwEVCt1jiZtuyPDCcmY0CP0HuHuzQel6aHBm4dlPMeVt1Bi73CXA46S9XyFk00SxV8fnxgWpWlzXEHlmx53kOW1L_1zj51vsAUHWYeLejdE4WtsaoudeSm7HqeQm9dikPYN2OIXX6IzZ8oWJocco2QxT-K7YHV_u4yjVVCEpAs44aHQQvMwzUxKGFVCUWNnzKVgecZnyoLUxg2GZRIUZVwLKt0g6Uwwx8fo-m-2AIDtvikq0_Tbwwv5N3heYdk</recordid><startdate>201005</startdate><enddate>201005</enddate><creator>Mauroux, P.-D</creator><creator>Virazel, A</creator><creator>Bosio, A</creator><creator>Dilillo, L</creator><creator>Girard, P</creator><creator>Pravossoudovitch, S</creator><creator>Godard, B</creator><creator>Festes, G</creator><creator>Vachez, L</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201005</creationdate><title>A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction</title><author>Mauroux, P.-D ; Virazel, A ; Bosio, A ; Dilillo, L ; Girard, P ; Pravossoudovitch, S ; Godard, B ; Festes, G ; Vachez, L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-3039484839bcab0217471ad62fbed3c367de58af483d25e71238415f71a8c42f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>coupling effects</topic><topic>defects</topic><topic>Dynamic programming</topic><topic>electrical model</topic><topic>embedded Flash</topic><topic>fault modeling</topic><topic>Flash memory</topic><topic>Fowler-Nordheim</topic><topic>Functional programming</topic><topic>Logic programming</topic><topic>Nonvolatile memory</topic><topic>Predictive models</topic><topic>Silicon</topic><topic>SPICE</topic><topic>Testing</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Mauroux, P.-D</creatorcontrib><creatorcontrib>Virazel, A</creatorcontrib><creatorcontrib>Bosio, A</creatorcontrib><creatorcontrib>Dilillo, L</creatorcontrib><creatorcontrib>Girard, P</creatorcontrib><creatorcontrib>Pravossoudovitch, S</creatorcontrib><creatorcontrib>Godard, B</creatorcontrib><creatorcontrib>Festes, G</creatorcontrib><creatorcontrib>Vachez, L</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mauroux, P.-D</au><au>Virazel, A</au><au>Bosio, A</au><au>Dilillo, L</au><au>Girard, P</au><au>Pravossoudovitch, S</au><au>Godard, B</au><au>Festes, G</au><au>Vachez, L</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction</atitle><btitle>2010 15th IEEE European Test Symposium</btitle><stitle>ETSYM</stitle><date>2010-05</date><risdate>2010</risdate><spage>81</spage><epage>86</epage><pages>81-86</pages><issn>1530-1877</issn><eissn>1558-1780</eissn><isbn>142445834X</isbn><isbn>9781424458349</isbn><eisbn>1424458358</eisbn><eisbn>9781424458332</eisbn><eisbn>1424458331</eisbn><eisbn>9781424458325</eisbn><eisbn>1424458323</eisbn><eisbn>9781424458356</eisbn><abstract>Flash memories are based on the floating gate technology allowing the write and erase data electronically. Such a technology can be prone to complex defects leading to faulty behaviors. In this paper, we introduce an electrical model of the ATMEL TSTACTM eFlash memory technology. The model is composed of two layers: a functional layer representing the floating gate and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model has been validated by means of simulations and comparisons with ATMEL silicon data. We apply this model for the analysis of defect-induced failures. As a case study, a resistive defect injection is considered.</abstract><pub>IEEE</pub><doi>10.1109/ETSYM.2010.5512776</doi><tpages>6</tpages></addata></record> |
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| issn | 1530-1877 1558-1780 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | coupling effects defects Dynamic programming electrical model embedded Flash fault modeling Flash memory Fowler-Nordheim Functional programming Logic programming Nonvolatile memory Predictive models Silicon SPICE Testing Voltage |
| title | A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction |
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