Smart power IC simulation of substrate coupled current due to majority and minority carriers transports
This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not t...
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| creator | Conte, Fabrizio Lo Sallese, Jean-Michel Kayal, Maher |
| description | This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components in the electrical design, the effect of substrate current is simulated. Having this information early in the design phase will allow design optimization and reduce the risk of costly chip redesign. |
| doi_str_mv | 10.1109/ICICDT.2010.5510262 |
| format | Conference Proceeding |
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Having this information early in the design phase will allow design optimization and reduce the risk of costly chip redesign.</description><subject>Circuit simulation</subject><subject>CMOS technology</subject><subject>Coupling circuits</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuit noise</subject><subject>Integrated circuit technology</subject><subject>Low voltage</subject><subject>Power integrated circuits</subject><subject>power parasitic modeling</subject><subject>power semiconductor devices</subject><subject>Semiconductor device noise</subject><subject>substrate modeling</subject><subject>Substrates</subject><subject>switching noise coupling</subject><issn>2381-3555</issn><issn>2691-0462</issn><isbn>9781424457731</isbn><isbn>1424457734</isbn><isbn>1424457742</isbn><isbn>9781424457755</isbn><isbn>1424457750</isbn><isbn>9781424457748</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1UEtrwzAY816wrusv6MV_IJ0_v30c2boFCjus9-I4znBpHtgOo_9-gXYnIQkJJITWQDYAxLxUZVW-7TeUzIIQQKikN-gJOOVcKMXpLVpQaaAgXNI7tDJK_3sM7mePaSiYEOIRrVI6EkIoIQACFujnu7Mx43H49RFXJU6hm042h6HHQ4vTVKccbfbYDdN48g12U4y-z7iZPM4D7uxxiCGfse0b3IX-QpyNMfiY8Jzt0zjEnJ7RQ2tPya-uuET77fu-_Cx2Xx9V-borgiG5MMxqyigQSQ04pnU7C85p3mhnJVN17VQNILninkvREkU4VXZe2zphHGNLtL7UBu_9YYxhXnc-XC9jf5QfXL0</recordid><startdate>201006</startdate><enddate>201006</enddate><creator>Conte, Fabrizio Lo</creator><creator>Sallese, Jean-Michel</creator><creator>Kayal, Maher</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201006</creationdate><title>Smart power IC simulation of substrate coupled current due to majority and minority carriers transports</title><author>Conte, Fabrizio Lo ; Sallese, Jean-Michel ; Kayal, Maher</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-93a8232106291c388f3a8cc84d8ca637bbc7b116474e465f070427a814fc59c33</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Circuit simulation</topic><topic>CMOS technology</topic><topic>Coupling circuits</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuit noise</topic><topic>Integrated circuit technology</topic><topic>Low voltage</topic><topic>Power integrated circuits</topic><topic>power parasitic modeling</topic><topic>power semiconductor devices</topic><topic>Semiconductor device noise</topic><topic>substrate modeling</topic><topic>Substrates</topic><topic>switching noise coupling</topic><toplevel>online_resources</toplevel><creatorcontrib>Conte, Fabrizio Lo</creatorcontrib><creatorcontrib>Sallese, Jean-Michel</creatorcontrib><creatorcontrib>Kayal, Maher</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Conte, Fabrizio Lo</au><au>Sallese, Jean-Michel</au><au>Kayal, Maher</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Smart power IC simulation of substrate coupled current due to majority and minority carriers transports</atitle><btitle>2010 IEEE International Conference on Integrated Circuit Design and Technology</btitle><stitle>ICICDT</stitle><date>2010-06</date><risdate>2010</risdate><spage>168</spage><epage>171</epage><pages>168-171</pages><issn>2381-3555</issn><eissn>2691-0462</eissn><isbn>9781424457731</isbn><isbn>1424457734</isbn><eisbn>1424457742</eisbn><eisbn>9781424457755</eisbn><eisbn>1424457750</eisbn><eisbn>9781424457748</eisbn><abstract>This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components in the electrical design, the effect of substrate current is simulated. Having this information early in the design phase will allow design optimization and reduce the risk of costly chip redesign.</abstract><pub>IEEE</pub><doi>10.1109/ICICDT.2010.5510262</doi><tpages>4</tpages></addata></record> |
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| ispartof | 2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010, p.168-171 |
| issn | 2381-3555 2691-0462 |
| language | eng |
| recordid | cdi_ieee_primary_5510262 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation CMOS technology Coupling circuits Integrated circuit modeling Integrated circuit noise Integrated circuit technology Low voltage Power integrated circuits power parasitic modeling power semiconductor devices Semiconductor device noise substrate modeling Substrates switching noise coupling |
| title | Smart power IC simulation of substrate coupled current due to majority and minority carriers transports |
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