An FPGA implementation of speech recognition with weighted finite state transducers

In this paper we present a hardware architecture for large vocabulary continuous speech recognition that conducts a search over a weighted finite state transducer (WFST) network. A pipelined architecture is proposed to fully utilize the memory bandwidth. A hash table is used to manage small sized wo...

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Bibliographische Detailangaben

Hauptverfasser:	Jungwook Choi, Kisun You, Wonyong Sung
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automata Bandwidth Character recognition Field programmable gate arrays FPGA Hardware Hidden Markov models Real time systems Speech recognition Transducers Vocabulary Weighted Finite State Transducer
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