A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies
In this paper a comparison of two low noise amplifiers (LNAs) designed in two 90 nm CMOS technologies (so called A and B) has been made. For each technology two LNA topologies were simulated: inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode...
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| creator | Gradzki, Jacek Borejko, Tomasz Pleskacz, Witold A |
| description | In this paper a comparison of two low noise amplifiers (LNAs) designed in two 90 nm CMOS technologies (so called A and B) has been made. For each technology two LNA topologies were simulated: inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with low supply voltage. These amplifiers were designed for a GPS/Galileo receiver. Chosen circuits demonstrate gains of 16.42 dB, 17.27 dB, 14.51 dB and 14.41 dB, consuming currents 2.492 mA, 3.093 mA, 2.834 mA and 4.609 mA with NFs equal to 1.881 dB, 1.914 dB, 2.345 dB and 2.427 dB for LC and FC architecture in A and B technologies respectively. For all amplifiers the supply voltage is 0.6 V. |
| doi_str_mv | 10.1109/DDECS.2010.5491783 |
| format | Conference Proceeding |
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For each technology two LNA topologies were simulated: inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with low supply voltage. These amplifiers were designed for a GPS/Galileo receiver. Chosen circuits demonstrate gains of 16.42 dB, 17.27 dB, 14.51 dB and 14.41 dB, consuming currents 2.492 mA, 3.093 mA, 2.834 mA and 4.609 mA with NFs equal to 1.881 dB, 1.914 dB, 2.345 dB and 2.427 dB for LC and FC architecture in A and B technologies respectively. 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For all amplifiers the supply voltage is 0.6 V.</description><subject>Circuit simulation</subject><subject>Circuit topology</subject><subject>CMOS technology</subject><subject>Gain</subject><subject>Global Positioning System</subject><subject>Low voltage</subject><subject>Low-noise amplifiers</subject><subject>Noise figure</subject><subject>Noise measurement</subject><subject>Satellite navigation systems</subject><isbn>9781424466122</isbn><isbn>1424466121</isbn><isbn>9781424466115</isbn><isbn>9781424466139</isbn><isbn>142446613X</isbn><isbn>1424466113</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVUM1KAzEYjIig1L6AXr4XaE2yyW5yLNtahdoetveSzU8b2d2UJLX49i7oxbkMAzMDMwg9ETwnBMuX5XJVN3OKR82ZJJUobtBUVoIwylhZEsJv_2lK79E0pU88gnGKS_GAugXo0J9V9CkMEBx04QpfocvqaGGzXYCK-uSz1fkSbQJjkz8O1oALEfpLl33KajAqGlhvmwb8APkaQGIYeqg_dg2M0dMQunD0Nj2iO6e6ZKd_PEH719W-fpttduv3erGZeYnzjKhStk7xSguqtBLGOeZUq5k0jPBWVoY7wjmxVIyjTCuqimqHWzo6FeFFMUHPv7XeWns4R9-r-H34u6j4AU1wWrc</recordid><startdate>201004</startdate><enddate>201004</enddate><creator>Gradzki, Jacek</creator><creator>Borejko, Tomasz</creator><creator>Pleskacz, Witold A</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201004</creationdate><title>A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies</title><author>Gradzki, Jacek ; Borejko, Tomasz ; Pleskacz, Witold A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-1a69bfa57c82aca8dff4fabc49d415b97d5f1551e28661db8772cf0b28dfa1533</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Circuit simulation</topic><topic>Circuit topology</topic><topic>CMOS technology</topic><topic>Gain</topic><topic>Global Positioning System</topic><topic>Low voltage</topic><topic>Low-noise amplifiers</topic><topic>Noise figure</topic><topic>Noise measurement</topic><topic>Satellite navigation systems</topic><toplevel>online_resources</toplevel><creatorcontrib>Gradzki, Jacek</creatorcontrib><creatorcontrib>Borejko, Tomasz</creatorcontrib><creatorcontrib>Pleskacz, Witold A</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gradzki, Jacek</au><au>Borejko, Tomasz</au><au>Pleskacz, Witold A</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies</atitle><btitle>13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems</btitle><stitle>DDECS</stitle><date>2010-04</date><risdate>2010</risdate><spage>213</spage><epage>216</epage><pages>213-216</pages><isbn>9781424466122</isbn><isbn>1424466121</isbn><eisbn>9781424466115</eisbn><eisbn>9781424466139</eisbn><eisbn>142446613X</eisbn><eisbn>1424466113</eisbn><abstract>In this paper a comparison of two low noise amplifiers (LNAs) designed in two 90 nm CMOS technologies (so called A and B) has been made. For each technology two LNA topologies were simulated: inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with low supply voltage. These amplifiers were designed for a GPS/Galileo receiver. Chosen circuits demonstrate gains of 16.42 dB, 17.27 dB, 14.51 dB and 14.41 dB, consuming currents 2.492 mA, 3.093 mA, 2.834 mA and 4.609 mA with NFs equal to 1.881 dB, 1.914 dB, 2.345 dB and 2.427 dB for LC and FC architecture in A and B technologies respectively. For all amplifiers the supply voltage is 0.6 V.</abstract><pub>IEEE</pub><doi>10.1109/DDECS.2010.5491783</doi><tpages>4</tpages></addata></record> |
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| ispartof | 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010, p.213-216 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation Circuit topology CMOS technology Gain Global Positioning System Low voltage Low-noise amplifiers Noise figure Noise measurement Satellite navigation systems |
| title | A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies |
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