Enabling 10µm pitch hybrid Cu-Cu IC stacking with Through Silicon Vias

Recently imec demonstrated for the first time 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV) on 200 mm wafers. The top tier dies are thinned down to 25 μm and bonded to the landing wafer by Cu-Cu thermo-compression. Nevertheless, the path towards high volu...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Huyghebaert, Cedric, Van Olmen, Jan, Chukwudi, Okoro, Coenen, Jens, Jourdain, Anne, Van Cauwenberghe, Marc, Agarwahl, Rahul, Phommahaxay, Alain, Stucchi, Michele, Soussan, Philippe
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Copper Dry etching Hybrid integrated circuits Integrated circuit interconnections Manufacturing Polymers Silicon Stacking Through-silicon vias Wafer bonding
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