Enabling 10µm pitch hybrid Cu-Cu IC stacking with Through Silicon Vias
Recently imec demonstrated for the first time 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV) on 200 mm wafers. The top tier dies are thinned down to 25 μm and bonded to the landing wafer by Cu-Cu thermo-compression. Nevertheless, the path towards high volu...
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| creator | Huyghebaert, Cedric Van Olmen, Jan Chukwudi, Okoro Coenen, Jens Jourdain, Anne Van Cauwenberghe, Marc Agarwahl, Rahul Phommahaxay, Alain Stucchi, Michele Soussan, Philippe |
| description | Recently imec demonstrated for the first time 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV) on 200 mm wafers. The top tier dies are thinned down to 25 μm and bonded to the landing wafer by Cu-Cu thermo-compression. Nevertheless, the path towards high volume manufacturing remains to be established. In this paper, we report about fundamental integration issues and discuss possible solutions for further process optimization. The implementation of the proposed solution substantially increased the electrical yield of Cu-Cu joining. |
| doi_str_mv | 10.1109/ECTC.2010.5490836 |
| format | Conference Proceeding |
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The top tier dies are thinned down to 25 μm and bonded to the landing wafer by Cu-Cu thermo-compression. Nevertheless, the path towards high volume manufacturing remains to be established. In this paper, we report about fundamental integration issues and discuss possible solutions for further process optimization. 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The top tier dies are thinned down to 25 μm and bonded to the landing wafer by Cu-Cu thermo-compression. Nevertheless, the path towards high volume manufacturing remains to be established. In this paper, we report about fundamental integration issues and discuss possible solutions for further process optimization. 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The top tier dies are thinned down to 25 μm and bonded to the landing wafer by Cu-Cu thermo-compression. Nevertheless, the path towards high volume manufacturing remains to be established. In this paper, we report about fundamental integration issues and discuss possible solutions for further process optimization. The implementation of the proposed solution substantially increased the electrical yield of Cu-Cu joining.</abstract><pub>IEEE</pub><doi>10.1109/ECTC.2010.5490836</doi></addata></record> |
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| identifier | ISSN: 0569-5503 |
| ispartof | 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 2010, p.1083-1087 |
| issn | 0569-5503 2377-5726 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Copper Dry etching Hybrid integrated circuits Integrated circuit interconnections Manufacturing Polymers Silicon Stacking Through-silicon vias Wafer bonding |
| title | Enabling 10µm pitch hybrid Cu-Cu IC stacking with Through Silicon Vias |
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