Three chips stacking with low volume solder using single re-flow process
Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip...
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creator | Khan, Navas Wee, David Ho Soon Ong Siong Chiew Sharmani, Cheryl Li Shiah Lim Hong Yu Li Vasarala, Shekar |
description | Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step. Three chips of 12mm × 12mm size with micro bumps at 100um pitch have been assembled using this approach. Low volume of lead free solder (Sn) has been chosen for the micro-bump interconnections between the chips. The thermal tacking conditions and flip-chip assembly process have been studied in details. The micro-joints quality and reliability have been assessed and reported. |
doi_str_mv | 10.1109/ECTC.2010.5490686 |
format | Conference Proceeding |
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Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step. Three chips of 12mm × 12mm size with micro bumps at 100um pitch have been assembled using this approach. Low volume of lead free solder (Sn) has been chosen for the micro-bump interconnections between the chips. The thermal tacking conditions and flip-chip assembly process have been studied in details. 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Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step. Three chips of 12mm × 12mm size with micro bumps at 100um pitch have been assembled using this approach. Low volume of lead free solder (Sn) has been chosen for the micro-bump interconnections between the chips. The thermal tacking conditions and flip-chip assembly process have been studied in details. The micro-joints quality and reliability have been assessed and reported.</description><subject>Assembly</subject><subject>Frequency</subject><subject>Lead</subject><subject>Microelectronics</subject><subject>Packaging</subject><subject>Stacking</subject><subject>Testing</subject><subject>Throughput</subject><subject>Tin</subject><subject>Wafer bonding</subject><issn>0569-5503</issn><issn>2377-5726</issn><isbn>9781424464104</isbn><isbn>1424464102</isbn><isbn>9781424464111</isbn><isbn>1424464110</isbn><isbn>1424464129</isbn><isbn>9781424464128</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVUMtOw0AQW14SVckHIC77AykzO7N5HFFUKFIlLuFcLZsJCaSkyqZU_D2N6AUfbFm2fLBStwgLRMjvl0VZLAwcreUckiw5U1GeZsiGOWFEPFczQ2ka29QkF_8y4Es1A5vksbVA1yoK4QOOYGsAcKZWZTOIaN-0u6DD6Pxn-_WuD-3Y6K4_6O--229Fh76rZND7MIUTdaIHieupsht6LyHcqKvadUGik87V6-OyLFbx-uXpuXhYxy2mdoyJGRmMI4uewFaSck2W8A29QG1qJm9dZnLKgdhL5YQq6ygxzlRsgGmu7v52WxHZ7IZ264afzekX-gVt2lEJ</recordid><startdate>201006</startdate><enddate>201006</enddate><creator>Khan, Navas</creator><creator>Wee, David Ho Soon</creator><creator>Ong Siong Chiew</creator><creator>Sharmani, Cheryl</creator><creator>Li Shiah Lim</creator><creator>Hong Yu Li</creator><creator>Vasarala, Shekar</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201006</creationdate><title>Three chips stacking with low volume solder using single re-flow process</title><author>Khan, Navas ; Wee, David Ho Soon ; Ong Siong Chiew ; Sharmani, Cheryl ; Li Shiah Lim ; Hong Yu Li ; Vasarala, Shekar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-3441402a351c305de74f3531b1ce0f2f43c5a82939034cedae3d5a362a2d42043</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Assembly</topic><topic>Frequency</topic><topic>Lead</topic><topic>Microelectronics</topic><topic>Packaging</topic><topic>Stacking</topic><topic>Testing</topic><topic>Throughput</topic><topic>Tin</topic><topic>Wafer bonding</topic><toplevel>online_resources</toplevel><creatorcontrib>Khan, Navas</creatorcontrib><creatorcontrib>Wee, David Ho Soon</creatorcontrib><creatorcontrib>Ong Siong Chiew</creatorcontrib><creatorcontrib>Sharmani, Cheryl</creatorcontrib><creatorcontrib>Li Shiah Lim</creatorcontrib><creatorcontrib>Hong Yu Li</creatorcontrib><creatorcontrib>Vasarala, Shekar</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Khan, Navas</au><au>Wee, David Ho Soon</au><au>Ong Siong Chiew</au><au>Sharmani, Cheryl</au><au>Li Shiah Lim</au><au>Hong Yu Li</au><au>Vasarala, Shekar</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Three chips stacking with low volume solder using single re-flow process</atitle><btitle>2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)</btitle><stitle>ECTC</stitle><date>2010-06</date><risdate>2010</risdate><spage>884</spage><epage>888</epage><pages>884-888</pages><issn>0569-5503</issn><eissn>2377-5726</eissn><isbn>9781424464104</isbn><isbn>1424464102</isbn><eisbn>9781424464111</eisbn><eisbn>1424464110</eisbn><eisbn>1424464129</eisbn><eisbn>9781424464128</eisbn><abstract>Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step. Three chips of 12mm × 12mm size with micro bumps at 100um pitch have been assembled using this approach. Low volume of lead free solder (Sn) has been chosen for the micro-bump interconnections between the chips. The thermal tacking conditions and flip-chip assembly process have been studied in details. The micro-joints quality and reliability have been assessed and reported.</abstract><pub>IEEE</pub><doi>10.1109/ECTC.2010.5490686</doi><tpages>5</tpages></addata></record> |
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ispartof | 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 2010, p.884-888 |
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subjects | Assembly Frequency Lead Microelectronics Packaging Stacking Testing Throughput Tin Wafer bonding |
title | Three chips stacking with low volume solder using single re-flow process |
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