Three chips stacking with low volume solder using single re-flow process

Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Khan, Navas, Wee, David Ho Soon, Ong Siong Chiew, Sharmani, Cheryl, Li Shiah Lim, Hong Yu Li, Vasarala, Shekar
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 888
container_issue
container_start_page 884
container_title
container_volume
creator Khan, Navas
Wee, David Ho Soon
Ong Siong Chiew
Sharmani, Cheryl
Li Shiah Lim
Hong Yu Li
Vasarala, Shekar
description Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step. Three chips of 12mm × 12mm size with micro bumps at 100um pitch have been assembled using this approach. Low volume of lead free solder (Sn) has been chosen for the micro-bump interconnections between the chips. The thermal tacking conditions and flip-chip assembly process have been studied in details. The micro-joints quality and reliability have been assessed and reported.
doi_str_mv 10.1109/ECTC.2010.5490686
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5490686</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5490686</ieee_id><sourcerecordid>5490686</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-3441402a351c305de74f3531b1ce0f2f43c5a82939034cedae3d5a362a2d42043</originalsourceid><addsrcrecordid>eNpVUMtOw0AQW14SVckHIC77AykzO7N5HFFUKFIlLuFcLZsJCaSkyqZU_D2N6AUfbFm2fLBStwgLRMjvl0VZLAwcreUckiw5U1GeZsiGOWFEPFczQ2ka29QkF_8y4Es1A5vksbVA1yoK4QOOYGsAcKZWZTOIaN-0u6DD6Pxn-_WuD-3Y6K4_6O--229Fh76rZND7MIUTdaIHieupsht6LyHcqKvadUGik87V6-OyLFbx-uXpuXhYxy2mdoyJGRmMI4uewFaSck2W8A29QG1qJm9dZnLKgdhL5YQq6ygxzlRsgGmu7v52WxHZ7IZ264afzekX-gVt2lEJ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Three chips stacking with low volume solder using single re-flow process</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Khan, Navas ; Wee, David Ho Soon ; Ong Siong Chiew ; Sharmani, Cheryl ; Li Shiah Lim ; Hong Yu Li ; Vasarala, Shekar</creator><creatorcontrib>Khan, Navas ; Wee, David Ho Soon ; Ong Siong Chiew ; Sharmani, Cheryl ; Li Shiah Lim ; Hong Yu Li ; Vasarala, Shekar</creatorcontrib><description>Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step. Three chips of 12mm × 12mm size with micro bumps at 100um pitch have been assembled using this approach. Low volume of lead free solder (Sn) has been chosen for the micro-bump interconnections between the chips. The thermal tacking conditions and flip-chip assembly process have been studied in details. The micro-joints quality and reliability have been assessed and reported.</description><identifier>ISSN: 0569-5503</identifier><identifier>ISBN: 9781424464104</identifier><identifier>ISBN: 1424464102</identifier><identifier>EISSN: 2377-5726</identifier><identifier>EISBN: 9781424464111</identifier><identifier>EISBN: 1424464110</identifier><identifier>EISBN: 1424464129</identifier><identifier>EISBN: 9781424464128</identifier><identifier>DOI: 10.1109/ECTC.2010.5490686</identifier><language>eng</language><publisher>IEEE</publisher><subject>Assembly ; Frequency ; Lead ; Microelectronics ; Packaging ; Stacking ; Testing ; Throughput ; Tin ; Wafer bonding</subject><ispartof>2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 2010, p.884-888</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5490686$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2053,27907,54902</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5490686$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Khan, Navas</creatorcontrib><creatorcontrib>Wee, David Ho Soon</creatorcontrib><creatorcontrib>Ong Siong Chiew</creatorcontrib><creatorcontrib>Sharmani, Cheryl</creatorcontrib><creatorcontrib>Li Shiah Lim</creatorcontrib><creatorcontrib>Hong Yu Li</creatorcontrib><creatorcontrib>Vasarala, Shekar</creatorcontrib><title>Three chips stacking with low volume solder using single re-flow process</title><title>2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)</title><addtitle>ECTC</addtitle><description>Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step. Three chips of 12mm × 12mm size with micro bumps at 100um pitch have been assembled using this approach. Low volume of lead free solder (Sn) has been chosen for the micro-bump interconnections between the chips. The thermal tacking conditions and flip-chip assembly process have been studied in details. The micro-joints quality and reliability have been assessed and reported.</description><subject>Assembly</subject><subject>Frequency</subject><subject>Lead</subject><subject>Microelectronics</subject><subject>Packaging</subject><subject>Stacking</subject><subject>Testing</subject><subject>Throughput</subject><subject>Tin</subject><subject>Wafer bonding</subject><issn>0569-5503</issn><issn>2377-5726</issn><isbn>9781424464104</isbn><isbn>1424464102</isbn><isbn>9781424464111</isbn><isbn>1424464110</isbn><isbn>1424464129</isbn><isbn>9781424464128</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVUMtOw0AQW14SVckHIC77AykzO7N5HFFUKFIlLuFcLZsJCaSkyqZU_D2N6AUfbFm2fLBStwgLRMjvl0VZLAwcreUckiw5U1GeZsiGOWFEPFczQ2ka29QkF_8y4Es1A5vksbVA1yoK4QOOYGsAcKZWZTOIaN-0u6DD6Pxn-_WuD-3Y6K4_6O--229Fh76rZND7MIUTdaIHieupsht6LyHcqKvadUGik87V6-OyLFbx-uXpuXhYxy2mdoyJGRmMI4uewFaSck2W8A29QG1qJm9dZnLKgdhL5YQq6ygxzlRsgGmu7v52WxHZ7IZ264afzekX-gVt2lEJ</recordid><startdate>201006</startdate><enddate>201006</enddate><creator>Khan, Navas</creator><creator>Wee, David Ho Soon</creator><creator>Ong Siong Chiew</creator><creator>Sharmani, Cheryl</creator><creator>Li Shiah Lim</creator><creator>Hong Yu Li</creator><creator>Vasarala, Shekar</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201006</creationdate><title>Three chips stacking with low volume solder using single re-flow process</title><author>Khan, Navas ; Wee, David Ho Soon ; Ong Siong Chiew ; Sharmani, Cheryl ; Li Shiah Lim ; Hong Yu Li ; Vasarala, Shekar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-3441402a351c305de74f3531b1ce0f2f43c5a82939034cedae3d5a362a2d42043</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Assembly</topic><topic>Frequency</topic><topic>Lead</topic><topic>Microelectronics</topic><topic>Packaging</topic><topic>Stacking</topic><topic>Testing</topic><topic>Throughput</topic><topic>Tin</topic><topic>Wafer bonding</topic><toplevel>online_resources</toplevel><creatorcontrib>Khan, Navas</creatorcontrib><creatorcontrib>Wee, David Ho Soon</creatorcontrib><creatorcontrib>Ong Siong Chiew</creatorcontrib><creatorcontrib>Sharmani, Cheryl</creatorcontrib><creatorcontrib>Li Shiah Lim</creatorcontrib><creatorcontrib>Hong Yu Li</creatorcontrib><creatorcontrib>Vasarala, Shekar</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Khan, Navas</au><au>Wee, David Ho Soon</au><au>Ong Siong Chiew</au><au>Sharmani, Cheryl</au><au>Li Shiah Lim</au><au>Hong Yu Li</au><au>Vasarala, Shekar</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Three chips stacking with low volume solder using single re-flow process</atitle><btitle>2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)</btitle><stitle>ECTC</stitle><date>2010-06</date><risdate>2010</risdate><spage>884</spage><epage>888</epage><pages>884-888</pages><issn>0569-5503</issn><eissn>2377-5726</eissn><isbn>9781424464104</isbn><isbn>1424464102</isbn><eisbn>9781424464111</eisbn><eisbn>1424464110</eisbn><eisbn>1424464129</eisbn><eisbn>9781424464128</eisbn><abstract>Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch micro-joints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step. Three chips of 12mm × 12mm size with micro bumps at 100um pitch have been assembled using this approach. Low volume of lead free solder (Sn) has been chosen for the micro-bump interconnections between the chips. The thermal tacking conditions and flip-chip assembly process have been studied in details. The micro-joints quality and reliability have been assessed and reported.</abstract><pub>IEEE</pub><doi>10.1109/ECTC.2010.5490686</doi><tpages>5</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0569-5503
ispartof 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 2010, p.884-888
issn 0569-5503
2377-5726
language eng
recordid cdi_ieee_primary_5490686
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Assembly
Frequency
Lead
Microelectronics
Packaging
Stacking
Testing
Throughput
Tin
Wafer bonding
title Three chips stacking with low volume solder using single re-flow process
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T09%3A34%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Three%20chips%20stacking%20with%20low%20volume%20solder%20using%20single%20re-flow%20process&rft.btitle=2010%20Proceedings%2060th%20Electronic%20Components%20and%20Technology%20Conference%20(ECTC)&rft.au=Khan,%20Navas&rft.date=2010-06&rft.spage=884&rft.epage=888&rft.pages=884-888&rft.issn=0569-5503&rft.eissn=2377-5726&rft.isbn=9781424464104&rft.isbn_list=1424464102&rft_id=info:doi/10.1109/ECTC.2010.5490686&rft_dat=%3Cieee_6IE%3E5490686%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424464111&rft.eisbn_list=1424464110&rft.eisbn_list=1424464129&rft.eisbn_list=9781424464128&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5490686&rfr_iscdi=true