Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter
We describe the area vs. performance tradeoffs for a Sigma Delta Modulated FIR filter designed with varying quantization levels. The FIR filter has been implemented in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of rep...
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| creator | Memon, Tayab D Beckett, Paul Sadik, Amin Z |
| description | We describe the area vs. performance tradeoffs for a Sigma Delta Modulated FIR filter designed with varying quantization levels. The FIR filter has been implemented in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. The synthesis results show the tradeoffs between hardware area and performance at varying quantization levels and at oversampling ratios of 32 and 64. Using a low-cost FPGA device the SQNR of the filter may be increased by 6-dB at the cost of a increased hardware but a reduction in FMAX of only about 10%. Typically, each doubling of OSR increases SQNR by over 9 dB at the cost of a doubling in hardware area. |
| doi_str_mv | 10.1109/ICMENS.2009.17 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5489383</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5489383</ieee_id><sourcerecordid>5489383</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-4405f214e91e4b3c79963ccc67f3674d3a679725dd5cda8a4b3c01f3c8a95da63</originalsourceid><addsrcrecordid>eNo1j81Kw0AYRUekoK3ZunEzL5A4k_nLtyyx1Uj8wQZclnHmmybSJjLJxreXoK4OFw4XDiHXnGWcM7ityqfN8y7LGYOMmzOy5DKXUmmu4ZwkYIr_reSCLGcNpADNLkgyjp-MMa5lAQIuyeMrxjDEk-0dpuuIljbRehxCGGnX06lFeodjd-jpEKilu3aIE30foqc19oeppdvqjW6744TxiiyCPY6Y_HFFmu2mKR_S-uW-Ktd12gGbUimZCjmXCBzlh3AGQAvnnDZBaCO9sNqAyZX3ynlb2NlhPAhXWFDearEiN7-3HSLuv2J3svF7r-aeQogf08tN-w</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Memon, Tayab D ; Beckett, Paul ; Sadik, Amin Z</creator><creatorcontrib>Memon, Tayab D ; Beckett, Paul ; Sadik, Amin Z</creatorcontrib><description>We describe the area vs. performance tradeoffs for a Sigma Delta Modulated FIR filter designed with varying quantization levels. The FIR filter has been implemented in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. The synthesis results show the tradeoffs between hardware area and performance at varying quantization levels and at oversampling ratios of 32 and 64. Using a low-cost FPGA device the SQNR of the filter may be increased by 6-dB at the cost of a increased hardware but a reduction in FMAX of only about 10%. Typically, each doubling of OSR increases SQNR by over 9 dB at the cost of a doubling in hardware area.</description><identifier>ISBN: 9781424456154</identifier><identifier>ISBN: 1424456150</identifier><identifier>ISBN: 0769539386</identifier><identifier>ISBN: 9780769539386</identifier><identifier>EISBN: 1424456169</identifier><identifier>EISBN: 9781424456161</identifier><identifier>DOI: 10.1109/ICMENS.2009.17</identifier><identifier>LCCN: 2009943960</identifier><language>eng</language><publisher>IEEE</publisher><subject>Costs ; Delta modulation ; Delta-sigma modulation ; Design engineering ; Field programmable gate arrays ; Finite impulse response filter ; Hardware ; NAME? ; Quantization ; Table lookup ; Transversal filters</subject><ispartof>2009 Fifth International Conference on MEMS NANO, and Smart Systems, 2009, p.67-71</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5489383$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5489383$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Memon, Tayab D</creatorcontrib><creatorcontrib>Beckett, Paul</creatorcontrib><creatorcontrib>Sadik, Amin Z</creatorcontrib><title>Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter</title><title>2009 Fifth International Conference on MEMS NANO, and Smart Systems</title><addtitle>ICMENS</addtitle><description>We describe the area vs. performance tradeoffs for a Sigma Delta Modulated FIR filter designed with varying quantization levels. The FIR filter has been implemented in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. The synthesis results show the tradeoffs between hardware area and performance at varying quantization levels and at oversampling ratios of 32 and 64. Using a low-cost FPGA device the SQNR of the filter may be increased by 6-dB at the cost of a increased hardware but a reduction in FMAX of only about 10%. Typically, each doubling of OSR increases SQNR by over 9 dB at the cost of a doubling in hardware area.</description><subject>Costs</subject><subject>Delta modulation</subject><subject>Delta-sigma modulation</subject><subject>Design engineering</subject><subject>Field programmable gate arrays</subject><subject>Finite impulse response filter</subject><subject>Hardware</subject><subject>NAME?</subject><subject>Quantization</subject><subject>Table lookup</subject><subject>Transversal filters</subject><isbn>9781424456154</isbn><isbn>1424456150</isbn><isbn>0769539386</isbn><isbn>9780769539386</isbn><isbn>1424456169</isbn><isbn>9781424456161</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j81Kw0AYRUekoK3ZunEzL5A4k_nLtyyx1Uj8wQZclnHmmybSJjLJxreXoK4OFw4XDiHXnGWcM7ityqfN8y7LGYOMmzOy5DKXUmmu4ZwkYIr_reSCLGcNpADNLkgyjp-MMa5lAQIuyeMrxjDEk-0dpuuIljbRehxCGGnX06lFeodjd-jpEKilu3aIE30foqc19oeppdvqjW6744TxiiyCPY6Y_HFFmu2mKR_S-uW-Ktd12gGbUimZCjmXCBzlh3AGQAvnnDZBaCO9sNqAyZX3ynlb2NlhPAhXWFDearEiN7-3HSLuv2J3svF7r-aeQogf08tN-w</recordid><startdate>200912</startdate><enddate>200912</enddate><creator>Memon, Tayab D</creator><creator>Beckett, Paul</creator><creator>Sadik, Amin Z</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200912</creationdate><title>Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter</title><author>Memon, Tayab D ; Beckett, Paul ; Sadik, Amin Z</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-4405f214e91e4b3c79963ccc67f3674d3a679725dd5cda8a4b3c01f3c8a95da63</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Costs</topic><topic>Delta modulation</topic><topic>Delta-sigma modulation</topic><topic>Design engineering</topic><topic>Field programmable gate arrays</topic><topic>Finite impulse response filter</topic><topic>Hardware</topic><topic>NAME?</topic><topic>Quantization</topic><topic>Table lookup</topic><topic>Transversal filters</topic><toplevel>online_resources</toplevel><creatorcontrib>Memon, Tayab D</creatorcontrib><creatorcontrib>Beckett, Paul</creatorcontrib><creatorcontrib>Sadik, Amin Z</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Memon, Tayab D</au><au>Beckett, Paul</au><au>Sadik, Amin Z</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter</atitle><btitle>2009 Fifth International Conference on MEMS NANO, and Smart Systems</btitle><stitle>ICMENS</stitle><date>2009-12</date><risdate>2009</risdate><spage>67</spage><epage>71</epage><pages>67-71</pages><isbn>9781424456154</isbn><isbn>1424456150</isbn><isbn>0769539386</isbn><isbn>9780769539386</isbn><eisbn>1424456169</eisbn><eisbn>9781424456161</eisbn><abstract>We describe the area vs. performance tradeoffs for a Sigma Delta Modulated FIR filter designed with varying quantization levels. The FIR filter has been implemented in VHDL using a hierarchical adder tree organization in both pipelined and non-pipelined modes and synthesized on a small number of representative commercial FPGA devices. The synthesis results show the tradeoffs between hardware area and performance at varying quantization levels and at oversampling ratios of 32 and 64. Using a low-cost FPGA device the SQNR of the filter may be increased by 6-dB at the cost of a increased hardware but a reduction in FMAX of only about 10%. Typically, each doubling of OSR increases SQNR by over 9 dB at the cost of a doubling in hardware area.</abstract><pub>IEEE</pub><doi>10.1109/ICMENS.2009.17</doi><tpages>5</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Costs Delta modulation Delta-sigma modulation Design engineering Field programmable gate arrays Finite impulse response filter Hardware NAME? Quantization Table lookup Transversal filters |
| title | Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-21T20%3A53%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Performance-Area%20Tradeoffs%20in%20the%20Design%20of%20a%20Short%20Word%20Length%20FIR%20Filter&rft.btitle=2009%20Fifth%20International%20Conference%20on%20MEMS%20NANO,%20and%20Smart%20Systems&rft.au=Memon,%20Tayab%20D&rft.date=2009-12&rft.spage=67&rft.epage=71&rft.pages=67-71&rft.isbn=9781424456154&rft.isbn_list=1424456150&rft.isbn_list=0769539386&rft.isbn_list=9780769539386&rft_id=info:doi/10.1109/ICMENS.2009.17&rft_dat=%3Cieee_6IE%3E5489383%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424456169&rft.eisbn_list=9781424456161&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5489383&rfr_iscdi=true |