Reliability constraints for TANOS memories due to alumina trapping and leakage
In this work we present a detailed investigation of TANOS memory reliability, focusing on issues raised by Al 2 O 3 trapping/detrapping and leakage. These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap...
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| creator | Amoroso, S M Mauri, A Galbiati, N Scozzari, C Mascellino, E Camozzi, E Rangoni, A Ghilardi, T Grossi, A Tessariol, P Compagnoni, C M Maconi, A Lacaita, A L Spinelli, A S Ghidini, G |
| description | In this work we present a detailed investigation of TANOS memory reliability, focusing on issues raised by Al 2 O 3 trapping/detrapping and leakage. These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al 2 O 3 charge storage modifies program and erase saturation level particularly when higher Al 2 O 3 thikness are considered. Threshold instability in early steps for endurance and retarded behavior for retention can be also ascribed to the Al 2 O 3 trapping. Moreover, Al 2 O 3 layer has been shown to provide the main leakage path for bottom oxides thickness in the 4.5 nm or above range. |
| doi_str_mv | 10.1109/IRPS.2010.5488694 |
| format | Conference Proceeding |
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These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al 2 O 3 charge storage modifies program and erase saturation level particularly when higher Al 2 O 3 thikness are considered. Threshold instability in early steps for endurance and retarded behavior for retention can be also ascribed to the Al 2 O 3 trapping. Moreover, Al 2 O 3 layer has been shown to provide the main leakage path for bottom oxides thickness in the 4.5 nm or above range.</description><subject>Capacitors</subject><subject>charge-trapping memories</subject><subject>Electron traps</subject><subject>Flash memories</subject><subject>high-k dielectrics</subject><subject>High-K gate dielectrics</subject><subject>Memory management</subject><subject>Nonvolatile memory</subject><subject>Parameter extraction</subject><subject>Research and development</subject><subject>Semiconductor device modeling</subject><subject>Stress</subject><subject>Temperature</subject><issn>1541-7026</issn><issn>1938-1891</issn><isbn>1424454301</isbn><isbn>9781424454303</isbn><isbn>1424454298</isbn><isbn>9781424454297</isbn><isbn>9781424454310</isbn><isbn>142445431X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9UNtqAjEUTC9Ct9YPKH3JD6zNSU42yaNIL4JoUd8lqyeSdm_srg_-fRcqnZdhmGFghrFnEFMA4V4Xm6_tVIpBarQ2c3jDHgElokbp7C1LwCmbgnVw928oAfeDoRFSI2Q2YomVaYZCgXpgk677FgNQywwxYasNFdHnsYj9hR_qqutbH6u-46Fu-W62Wm95SWXdRur48Uy8r7kvzmWsPB-STROrE_fVkRfkf_yJntgo-KKjyZXHbPf-tpt_psv1x2I-W6YRjO5TyE04IoK00pBTxgRJxsmDUIEAnXWZRQW5tmGY5iioXGhhVNB6yGRejdnLX20kon3TxtK3l_31IvULG9dS-Q</recordid><startdate>201005</startdate><enddate>201005</enddate><creator>Amoroso, S M</creator><creator>Mauri, A</creator><creator>Galbiati, N</creator><creator>Scozzari, C</creator><creator>Mascellino, E</creator><creator>Camozzi, E</creator><creator>Rangoni, A</creator><creator>Ghilardi, T</creator><creator>Grossi, A</creator><creator>Tessariol, P</creator><creator>Compagnoni, C M</creator><creator>Maconi, A</creator><creator>Lacaita, A L</creator><creator>Spinelli, A S</creator><creator>Ghidini, G</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201005</creationdate><title>Reliability constraints for TANOS memories due to alumina trapping and leakage</title><author>Amoroso, S M ; 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These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al 2 O 3 charge storage modifies program and erase saturation level particularly when higher Al 2 O 3 thikness are considered. Threshold instability in early steps for endurance and retarded behavior for retention can be also ascribed to the Al 2 O 3 trapping. Moreover, Al 2 O 3 layer has been shown to provide the main leakage path for bottom oxides thickness in the 4.5 nm or above range.</abstract><pub>IEEE</pub><doi>10.1109/IRPS.2010.5488694</doi><tpages>4</tpages></addata></record> |
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| issn | 1541-7026 1938-1891 |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitors charge-trapping memories Electron traps Flash memories high-k dielectrics High-K gate dielectrics Memory management Nonvolatile memory Parameter extraction Research and development Semiconductor device modeling Stress Temperature |
| title | Reliability constraints for TANOS memories due to alumina trapping and leakage |
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