Concurrency Reduction of Untimed Latch Protocols - Theory and Practice

A systematic investigation into concurrency reduction of untimed asynchronous 4-phase latch controllers is reported. Starting with a state graph that exhibits maximal concurrency, rules are provided for systematically reducing its states and thereby curtailing its behaviors. The rules predict livene...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Varanasi, Santosh N, Stevens, Kenneth S, Birtwistle, Graham
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Asynchronous circuits Asynchronous Design Computer science Concurrency Reduction Concurrent computing Control systems Decoding Latches Microprocessors Pipeline processing pipelining Protocols Signal design Synchronization verification
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