How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining

Fault-tolerant clocking schemes become inevitable when it comes to highly-reliable chip designs. Because of the additional hardware overhead, existing solutions are considerably slower than their non-reliable counterparts. In this paper, we demonstrate that pipelining is a viable approach to speed u...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Függer, Matthias, Dielacher, Andreas, Schmid, Ulrich
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis Chip scale packaging clock synchronization Clocks Distributed algorithms Fault tolerance Fault tolerant systems Fault-tolerant distributed algorithms Hardware modeling approaches Performance analysis Pipeline processing pipelining Very large scale integration VLSI
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