Implementing the Himeno benchmark with CUDA on GPU clusters
This paper describes the use of CUDA to accelerate the Himeno benchmark on clusters with GPUs. The implementation is designed to optimize memory bandwidth utilization. Our approach achieves over 83% of the theoretical peak bandwidth on a NVIDIA Tesla C1060 GPU and performs at over 50 GFlops. A multi...
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| creator | Phillips, Everett H Fatica, Massimiliano |
| description | This paper describes the use of CUDA to accelerate the Himeno benchmark on clusters with GPUs. The implementation is designed to optimize memory bandwidth utilization. Our approach achieves over 83% of the theoretical peak bandwidth on a NVIDIA Tesla C1060 GPU and performs at over 50 GFlops. A multi-GPU implementation that utilizes MPI alongside CUDA streams to overlap GPU execution with data transfers allows linear scaling and performs at over 800 GFlops on a cluster with 16 GPUs. The paper presents the optimizations required to achieve this level of performance. |
| doi_str_mv | 10.1109/IPDPS.2010.5470394 |
| format | Conference Proceeding |
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The paper presents the optimizations required to achieve this level of performance.</description><subject>Acceleration</subject><subject>Bandwidth</subject><subject>Clocks</subject><subject>Convergence</subject><subject>Design optimization</subject><subject>Frequency</subject><subject>Kernel</subject><subject>Navier-Stokes equations</subject><subject>Poisson equations</subject><subject>Throughput</subject><issn>1530-2075</issn><isbn>1424464420</isbn><isbn>9781424464425</isbn><isbn>1424464412</isbn><isbn>1424464439</isbn><isbn>9781424464418</isbn><isbn>9781424464432</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFj0FLw0AUhFdUsNb-Ab3sH0h9-3Y3m8VTSbUNFAzYnkuyfWtWk7QkEfHfG7DgHGb4LsMMY_cC5kKAfczyZf42RxhZKwPSqgt2KxQqFSsl8PIfEK7YRGgJEYLRN2zW9x8wSmmMBUzYU9acamqoHUL7zoeK-DqMdOQlta5qiu6Tf4eh4uluueDHlq_yHXf1Vz9Q19-xa1_UPc3OOWXbl-dtuo42r6ssXWyiYGGIfAEOjSgQlND6oEosbexkYkWi0YxuvHWeqPTey6TQThuIXYzOeNIHreSUPfzVBiLan7owrvrZn3_LX82eSNE</recordid><startdate>201004</startdate><enddate>201004</enddate><creator>Phillips, Everett H</creator><creator>Fatica, Massimiliano</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201004</creationdate><title>Implementing the Himeno benchmark with CUDA on GPU clusters</title><author>Phillips, Everett H ; Fatica, Massimiliano</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-fa0c271a204155d4b2b96c389185279187f9cfeebfff38a5c5706c62c7fe5d543</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Acceleration</topic><topic>Bandwidth</topic><topic>Clocks</topic><topic>Convergence</topic><topic>Design optimization</topic><topic>Frequency</topic><topic>Kernel</topic><topic>Navier-Stokes equations</topic><topic>Poisson equations</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Phillips, Everett H</creatorcontrib><creatorcontrib>Fatica, Massimiliano</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Phillips, Everett H</au><au>Fatica, Massimiliano</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Implementing the Himeno benchmark with CUDA on GPU clusters</atitle><btitle>2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)</btitle><stitle>IPDPS</stitle><date>2010-04</date><risdate>2010</risdate><spage>1</spage><epage>10</epage><pages>1-10</pages><issn>1530-2075</issn><isbn>1424464420</isbn><isbn>9781424464425</isbn><eisbn>1424464412</eisbn><eisbn>1424464439</eisbn><eisbn>9781424464418</eisbn><eisbn>9781424464432</eisbn><abstract>This paper describes the use of CUDA to accelerate the Himeno benchmark on clusters with GPUs. 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| ispartof | 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 2010, p.1-10 |
| issn | 1530-2075 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Acceleration Bandwidth Clocks Convergence Design optimization Frequency Kernel Navier-Stokes equations Poisson equations Throughput |
| title | Implementing the Himeno benchmark with CUDA on GPU clusters |
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