Design of multiplierless FIR filters with an adder depth versus filter order trade-off
In this work, the trade-offs in FIR filter design are studied. This includes the adder depth for the constant filter coefficients, the number of adders, and the number of delay elements, i.e., the filter order. It is shown that the proposed design algorithm can be used to decrease both the overall a...
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| creator | Johansson, Kenny DeBrunner, Linda S Gustafsson, Oscar DeBrunner, Victor |
| description | In this work, the trade-offs in FIR filter design are studied. This includes the adder depth for the constant filter coefficients, the number of adders, and the number of delay elements, i.e., the filter order. It is shown that the proposed design algorithm can be used to decrease both the overall arithmetic complexity and the adder depth, possibly with a small penalty in delay elements. This is achieved by selecting coefficients that can be realized at a lower depth, i.e., the lengths of the logic paths are reduced. Hence, this directly translates into decreased power consumption due to reduced glitch propagation and increased throughput due to a shorter critical path. |
| doi_str_mv | 10.1109/ACSSC.2009.5469952 |
| format | Conference Proceeding |
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| ispartof | 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers, 2009, p.744-748 |
| issn | 1058-6393 2576-2303 |
| language | eng |
| recordid | cdi_ieee_primary_5469952 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Arithmetic Delay Digital signal processing Electronic mail Energy consumption Finite impulse response filter Logic Signal processing algorithms Throughput |
| title | Design of multiplierless FIR filters with an adder depth versus filter order trade-off |
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