Defect diagnosis based on DFM guidelines
Following design-for-manufacturability (DFM) guidelines during chip design can lower the possibility of occurrence of systematic defects. In this paper, we investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for...
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creator | Dongok Kim Pomeranz, Irith Amyeen, M Enamul Venkataraman, Srikanth |
description | Following design-for-manufacturability (DFM) guidelines during chip design can lower the possibility of occurrence of systematic defects. In this paper, we investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for the defects present in failing chips. We also introduce a new metric called diagnostic coefficient that allows us to rank the guidelines according to their contribution of hard-to-diagnose defects. DFM guidelines that are ranked high should be applied during chip design in order to obtain chips that are easier to diagnose. |
doi_str_mv | 10.1109/VTS.2010.5469577 |
format | Conference Proceeding |
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DFM guidelines that are ranked high should be applied during chip design in order to obtain chips that are easier to diagnose.</description><subject>Chip scale packaging</subject><subject>Design for manufacture</subject><subject>Failure analysis</subject><subject>Fault diagnosis</subject><subject>Guidelines</subject><subject>Manufacturing processes</subject><subject>Process design</subject><subject>Switches</subject><subject>Testing</subject><subject>Very large scale integration</subject><issn>1093-0167</issn><issn>2375-1053</issn><isbn>9781424466498</isbn><isbn>1424466490</isbn><isbn>9781424466481</isbn><isbn>1424466504</isbn><isbn>9781424466504</isbn><isbn>1424466482</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVjztLA0EUhccXuMb0gs2WNhPvvTvPUhJjAhELF9swszMTRuJGMrHw32fBNFaHw4GP7zB2hzBBBPv40b5PCIYmhbJS6zM2ttqgICGUEgbPWUWNlhxBNhf_NmsuWTUgGg6o9DW7KeUTgEAKqNjDLKbYHeqQ3abflVxq70oM9a6vZ_PXevOTQ9zmPpZbdpXctsTxKUesnT-30wVfvb0sp08rni0ceADtLOlkgUikNKjaLnknUpCAJqB1hDoo8lKEYKTvqFOoU6QkcFD1zYjd_2FzjHH9vc9fbv-7Pn1ujgscRCo</recordid><startdate>201004</startdate><enddate>201004</enddate><creator>Dongok Kim</creator><creator>Pomeranz, Irith</creator><creator>Amyeen, M Enamul</creator><creator>Venkataraman, Srikanth</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201004</creationdate><title>Defect diagnosis based on DFM guidelines</title><author>Dongok Kim ; Pomeranz, Irith ; Amyeen, M Enamul ; Venkataraman, Srikanth</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-d07a927f90224ff4699cfba4fd5018d19a217d62b54dd85bc2c617fe2f41664b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Chip scale packaging</topic><topic>Design for manufacture</topic><topic>Failure analysis</topic><topic>Fault diagnosis</topic><topic>Guidelines</topic><topic>Manufacturing processes</topic><topic>Process design</topic><topic>Switches</topic><topic>Testing</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Dongok Kim</creatorcontrib><creatorcontrib>Pomeranz, Irith</creatorcontrib><creatorcontrib>Amyeen, M Enamul</creatorcontrib><creatorcontrib>Venkataraman, Srikanth</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dongok Kim</au><au>Pomeranz, Irith</au><au>Amyeen, M Enamul</au><au>Venkataraman, Srikanth</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Defect diagnosis based on DFM guidelines</atitle><btitle>2010 28th VLSI Test Symposium (VTS)</btitle><stitle>VTS</stitle><date>2010-04</date><risdate>2010</risdate><spage>206</spage><epage>211</epage><pages>206-211</pages><issn>1093-0167</issn><eissn>2375-1053</eissn><isbn>9781424466498</isbn><isbn>1424466490</isbn><eisbn>9781424466481</eisbn><eisbn>1424466504</eisbn><eisbn>9781424466504</eisbn><eisbn>1424466482</eisbn><abstract>Following design-for-manufacturability (DFM) guidelines during chip design can lower the possibility of occurrence of systematic defects. In this paper, we investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for the defects present in failing chips. We also introduce a new metric called diagnostic coefficient that allows us to rank the guidelines according to their contribution of hard-to-diagnose defects. DFM guidelines that are ranked high should be applied during chip design in order to obtain chips that are easier to diagnose.</abstract><pub>IEEE</pub><doi>10.1109/VTS.2010.5469577</doi><tpages>6</tpages></addata></record> |
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subjects | Chip scale packaging Design for manufacture Failure analysis Fault diagnosis Guidelines Manufacturing processes Process design Switches Testing Very large scale integration |
title | Defect diagnosis based on DFM guidelines |
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