A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits
This paper describes a new procedure for estimating the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical techniques to take advantage of their time-efficiency over conventional logic simulators. Combinational circuits driven by s...
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creator | Yong Je Lim Kyung-Im Son Heung-Joon Park Soma, M. |
description | This paper describes a new procedure for estimating the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical techniques to take advantage of their time-efficiency over conventional logic simulators. Combinational circuits driven by synchronized logic signals are considered as application targets and the statistical properties of logic signals and circuit parameters are defined and evaluated. The experimental result on benchmark circuits shows the significant time efficiency of the proposed procedure. |
doi_str_mv | 10.1109/DAC.1996.545617 |
format | Conference Proceeding |
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The procedure is based on analytic and statistical techniques to take advantage of their time-efficiency over conventional logic simulators. Combinational circuits driven by synchronized logic signals are considered as application targets and the statistical properties of logic signals and circuit parameters are defined and evaluated. The experimental result on benchmark circuits shows the significant time efficiency of the proposed procedure.</description><identifier>ISSN: 0738-100X</identifier><identifier>ISBN: 0780332946</identifier><identifier>ISBN: 9780780332942</identifier><identifier>DOI: 10.1109/DAC.1996.545617</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; CMOS logic circuits ; Combinational circuits ; Delay estimation ; Density measurement ; Permission ; Pipeline processing ; Power dissipation ; Pulse width modulation ; Switching circuits</subject><ispartof>33rd Design Automation Conference Proceedings, 1996, 1996, p.445-450</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/545617$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,796,2058,4050,4051,27925,54758,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/545617$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yong Je Lim</creatorcontrib><creatorcontrib>Kyung-Im Son</creatorcontrib><creatorcontrib>Heung-Joon Park</creatorcontrib><creatorcontrib>Soma, M.</creatorcontrib><title>A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits</title><title>33rd Design Automation Conference Proceedings, 1996</title><addtitle>DAC</addtitle><description>This paper describes a new procedure for estimating the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical techniques to take advantage of their time-efficiency over conventional logic simulators. Combinational circuits driven by synchronized logic signals are considered as application targets and the statistical properties of logic signals and circuit parameters are defined and evaluated. The experimental result on benchmark circuits shows the significant time efficiency of the proposed procedure.</description><subject>Circuit simulation</subject><subject>CMOS logic circuits</subject><subject>Combinational circuits</subject><subject>Delay estimation</subject><subject>Density measurement</subject><subject>Permission</subject><subject>Pipeline processing</subject><subject>Power dissipation</subject><subject>Pulse width modulation</subject><subject>Switching circuits</subject><issn>0738-100X</issn><isbn>0780332946</isbn><isbn>9780780332942</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9j71uwkAQhE9KkMJfjZRqX8BmLzY2LpFDRINShCIdOs4L3sjcWb6FiLfHSlKnGmk-zYxGqZnGWGss5q-rMtZFkcWLdJHp_EGNMF9ikrwUafaohpgny0gjfj6pUQhfiJjqTA-VX0EQIxyErWnAtG3nja1BPEhNQL1_7rF34I9QUWNuUUUtuYqcQPhmsTW7ExgrfGVhCsAOyu37B1h_PrD7yfbFljt7YQkTNTiaJtD0T8fq-W29KzcRE9G-7fq17rb__ZD8C-97Xksw</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Yong Je Lim</creator><creator>Kyung-Im Son</creator><creator>Heung-Joon Park</creator><creator>Soma, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1996</creationdate><title>A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits</title><author>Yong Je Lim ; Kyung-Im Son ; Heung-Joon Park ; Soma, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_5456173</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Circuit simulation</topic><topic>CMOS logic circuits</topic><topic>Combinational circuits</topic><topic>Delay estimation</topic><topic>Density measurement</topic><topic>Permission</topic><topic>Pipeline processing</topic><topic>Power dissipation</topic><topic>Pulse width modulation</topic><topic>Switching circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Yong Je Lim</creatorcontrib><creatorcontrib>Kyung-Im Son</creatorcontrib><creatorcontrib>Heung-Joon Park</creatorcontrib><creatorcontrib>Soma, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yong Je Lim</au><au>Kyung-Im Son</au><au>Heung-Joon Park</au><au>Soma, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits</atitle><btitle>33rd Design Automation Conference Proceedings, 1996</btitle><stitle>DAC</stitle><date>1996</date><risdate>1996</risdate><spage>445</spage><epage>450</epage><pages>445-450</pages><issn>0738-100X</issn><isbn>0780332946</isbn><isbn>9780780332942</isbn><abstract>This paper describes a new procedure for estimating the delay-dependent switching activities in CMOS combinational circuits. The procedure is based on analytic and statistical techniques to take advantage of their time-efficiency over conventional logic simulators. Combinational circuits driven by synchronized logic signals are considered as application targets and the statistical properties of logic signals and circuit parameters are defined and evaluated. The experimental result on benchmark circuits shows the significant time efficiency of the proposed procedure.</abstract><pub>IEEE</pub><doi>10.1109/DAC.1996.545617</doi></addata></record> |
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identifier | ISSN: 0738-100X |
ispartof | 33rd Design Automation Conference Proceedings, 1996, 1996, p.445-450 |
issn | 0738-100X |
language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Circuit simulation CMOS logic circuits Combinational circuits Delay estimation Density measurement Permission Pipeline processing Power dissipation Pulse width modulation Switching circuits |
title | A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits |
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