0.5 μm CMOS Device Design and Characterization

The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n + polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control channel hot elect...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hanafi, H. I., Wordeman, M. R., Wang, L. K., Taur, Y., Sun, J. Y. C., Dennard, R. H., Zicherman, D. S., Rodriguez, M. D., Haddad, N., Edenfeld, A., Polavarapu, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Degradation Delay Doping profiles Electrical resistance measurement Electrodes Electrons Inverters Power supplies Silicides Titanium
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