200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology
In order to achieve 0.25 μm CMOS devices with industrial transfer capability, a 8" DUV lithography cell has been installed, including a 5500/90 ASM-L DUV stepper and a TEL Mark 8 track. An original physico-chemical screening test, based on DSC, allows us to select optimized DUV positive materia...
Gespeichert in:
| Hauptverfasser: | , , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 126 |
|---|---|
| container_issue | |
| container_start_page | 123 |
| container_title | |
| container_volume | |
| creator | Vinet, F. Buffet, N. Le Cornec, Ch Lerme, M. Morand, Y. Mourier, T. Previtali, B Paniez, P. J. |
| description | In order to achieve 0.25 μm CMOS devices with industrial transfer capability, a 8" DUV lithography cell has been installed, including a 5500/90 ASM-L DUV stepper and a TEL Mark 8 track. An original physico-chemical screening test, based on DSC, allows us to select optimized DUV positive materials regarding to delay, environment and substrate sensitivity. Process optimization with selected materials has been performed and implemented on 0.25 μm CMOS technology. Process latitudes as well as electrical results are presented. |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5435996</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5435996</ieee_id><sourcerecordid>5435996</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-c6edcaad6408153a56d998eb721f679e2e9e34569a22571cf4cb6893361163533</originalsourceid><addsrcrecordid>eNotzE1OhDAYgOEmxkQzcgI33wUw_aGln7sJ_iZMMBHdTkopQw1QAt3g2TyDZ3Ixrt5n9V6QBHPNtRKCM83xiiTr-kUpZaiQZfKaNJxSGEd4-PiE0sc-nBYz9xvcw8FEt3gzgJlaeFuCdesK1Rz96L9N9GGC_TwP3p4dA9A7LuH3Z4TiUL1D7Ww_hSGcthty2Zlhdcl_d6R-eqyLl7Ssnl-LfZl6pDG1yrXWmFZlVDMpjFQtonZNzlmncnTcoROZVGg4lzmzXWYbpVEIxZgSUogduT1vvXPuOC9-NMt2lJmQiEr8Af6QTL0</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Vinet, F. ; Buffet, N. ; Le Cornec, Ch ; Lerme, M. ; Morand, Y. ; Mourier, T. ; Previtali, B ; Paniez, P. J.</creator><creatorcontrib>Vinet, F. ; Buffet, N. ; Le Cornec, Ch ; Lerme, M. ; Morand, Y. ; Mourier, T. ; Previtali, B ; Paniez, P. J.</creatorcontrib><description>In order to achieve 0.25 μm CMOS devices with industrial transfer capability, a 8" DUV lithography cell has been installed, including a 5500/90 ASM-L DUV stepper and a TEL Mark 8 track. An original physico-chemical screening test, based on DSC, allows us to select optimized DUV positive materials regarding to delay, environment and substrate sensitivity. Process optimization with selected materials has been performed and implemented on 0.25 μm CMOS technology. Process latitudes as well as electrical results are presented.</description><identifier>ISBN: 9782863321829</identifier><identifier>ISBN: 286332182X</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS process ; CMOS technology ; Delay effects ; Lithography ; Optical materials ; Resists ; Temperature ; Thermal resistance ; Tin ; Windows</subject><ispartof>ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference, 1995, p.123-126</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5435996$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5435996$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Vinet, F.</creatorcontrib><creatorcontrib>Buffet, N.</creatorcontrib><creatorcontrib>Le Cornec, Ch</creatorcontrib><creatorcontrib>Lerme, M.</creatorcontrib><creatorcontrib>Morand, Y.</creatorcontrib><creatorcontrib>Mourier, T.</creatorcontrib><creatorcontrib>Previtali, B</creatorcontrib><creatorcontrib>Paniez, P. J.</creatorcontrib><title>200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology</title><title>ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference</title><addtitle>ESSDERC</addtitle><description>In order to achieve 0.25 μm CMOS devices with industrial transfer capability, a 8" DUV lithography cell has been installed, including a 5500/90 ASM-L DUV stepper and a TEL Mark 8 track. An original physico-chemical screening test, based on DSC, allows us to select optimized DUV positive materials regarding to delay, environment and substrate sensitivity. Process optimization with selected materials has been performed and implemented on 0.25 μm CMOS technology. Process latitudes as well as electrical results are presented.</description><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Delay effects</subject><subject>Lithography</subject><subject>Optical materials</subject><subject>Resists</subject><subject>Temperature</subject><subject>Thermal resistance</subject><subject>Tin</subject><subject>Windows</subject><isbn>9782863321829</isbn><isbn>286332182X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotzE1OhDAYgOEmxkQzcgI33wUw_aGln7sJ_iZMMBHdTkopQw1QAt3g2TyDZ3Ixrt5n9V6QBHPNtRKCM83xiiTr-kUpZaiQZfKaNJxSGEd4-PiE0sc-nBYz9xvcw8FEt3gzgJlaeFuCdesK1Rz96L9N9GGC_TwP3p4dA9A7LuH3Z4TiUL1D7Ww_hSGcthty2Zlhdcl_d6R-eqyLl7Ssnl-LfZl6pDG1yrXWmFZlVDMpjFQtonZNzlmncnTcoROZVGg4lzmzXWYbpVEIxZgSUogduT1vvXPuOC9-NMt2lJmQiEr8Af6QTL0</recordid><startdate>199509</startdate><enddate>199509</enddate><creator>Vinet, F.</creator><creator>Buffet, N.</creator><creator>Le Cornec, Ch</creator><creator>Lerme, M.</creator><creator>Morand, Y.</creator><creator>Mourier, T.</creator><creator>Previtali, B</creator><creator>Paniez, P. J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>199509</creationdate><title>200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology</title><author>Vinet, F. ; Buffet, N. ; Le Cornec, Ch ; Lerme, M. ; Morand, Y. ; Mourier, T. ; Previtali, B ; Paniez, P. J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-c6edcaad6408153a56d998eb721f679e2e9e34569a22571cf4cb6893361163533</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Delay effects</topic><topic>Lithography</topic><topic>Optical materials</topic><topic>Resists</topic><topic>Temperature</topic><topic>Thermal resistance</topic><topic>Tin</topic><topic>Windows</topic><toplevel>online_resources</toplevel><creatorcontrib>Vinet, F.</creatorcontrib><creatorcontrib>Buffet, N.</creatorcontrib><creatorcontrib>Le Cornec, Ch</creatorcontrib><creatorcontrib>Lerme, M.</creatorcontrib><creatorcontrib>Morand, Y.</creatorcontrib><creatorcontrib>Mourier, T.</creatorcontrib><creatorcontrib>Previtali, B</creatorcontrib><creatorcontrib>Paniez, P. J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vinet, F.</au><au>Buffet, N.</au><au>Le Cornec, Ch</au><au>Lerme, M.</au><au>Morand, Y.</au><au>Mourier, T.</au><au>Previtali, B</au><au>Paniez, P. J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology</atitle><btitle>ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference</btitle><stitle>ESSDERC</stitle><date>1995-09</date><risdate>1995</risdate><spage>123</spage><epage>126</epage><pages>123-126</pages><isbn>9782863321829</isbn><isbn>286332182X</isbn><abstract>In order to achieve 0.25 μm CMOS devices with industrial transfer capability, a 8" DUV lithography cell has been installed, including a 5500/90 ASM-L DUV stepper and a TEL Mark 8 track. An original physico-chemical screening test, based on DSC, allows us to select optimized DUV positive materials regarding to delay, environment and substrate sensitivity. Process optimization with selected materials has been performed and implemented on 0.25 μm CMOS technology. Process latitudes as well as electrical results are presented.</abstract><pub>IEEE</pub><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9782863321829 |
| ispartof | ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference, 1995, p.123-126 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_5435996 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS process CMOS technology Delay effects Lithography Optical materials Resists Temperature Thermal resistance Tin Windows |
| title | 200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T06%3A08%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=200%20mm%20DUV%20Lithography%20:%20Material%20and%20Process%20Optimization%20Application%20to%200.25%20%CE%BCm%20CMOS%20Technology&rft.btitle=ESSDERC%20'95:%20Proceedings%20of%20the%2025th%20European%20Solid%20State%20Device%20Research%20Conference&rft.au=Vinet,%20F.&rft.date=1995-09&rft.spage=123&rft.epage=126&rft.pages=123-126&rft.isbn=9782863321829&rft.isbn_list=286332182X&rft_id=info:doi/&rft_dat=%3Cieee_6IE%3E5435996%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5435996&rfr_iscdi=true |