A Fast Two-Bit Quantiser for Use in High Speed A to D Converter Systems
This paper describes a two-bit quantiser for use in A to D converters operating at sample rates up to 100 MHz. The performance in a 5-bit all parallel system is reported.
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| creator | Fryers, A.J. |
| description | This paper describes a two-bit quantiser for use in A to D converters operating at sample rates up to 100 MHz. The performance in a 5-bit all parallel system is reported. |
| format | Conference Proceeding |
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The performance in a 5-bit all parallel system is reported.</description><subject>Circuits</subject><subject>Computational modeling</subject><subject>Encoding</subject><subject>Feedback</subject><subject>Latches</subject><subject>Logic arrays</subject><subject>Propagation delay</subject><subject>Sampling methods</subject><subject>System-on-a-chip</subject><subject>Voltage</subject><isbn>9783800711321</isbn><isbn>380071132X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1977</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotzMFKw0AQgOEFEZSaJ_AyLxCYzexms8dYbSsURBrPZZLO6opNSnZV-vYKevovH_-FKrxrqEF0WlOlr1SR0jsial97bcy1Wrew4pSh-57Ku5jh-ZPHHJPMEKYZXpJAHGETX99gdxI5QAt5gntYTuOXzPmX7c4pyzHdqMvAH0mK_y5Ut3rolpty-7R-XLbbMnrMpdO9twZr37BmZjJVsL21DZEnRjaHoeoHDKFxwYZght4RDrV47TxZ4kALdfu3jSKyP83xyPN5bw1ZrA39ANN2QyY</recordid><startdate>197709</startdate><enddate>197709</enddate><creator>Fryers, A.J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>197709</creationdate><title>A Fast Two-Bit Quantiser for Use in High Speed A to D Converter Systems</title><author>Fryers, A.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-71b9540698a1aaa342f5b5583393a0a4dc2bc0ff87f5ff4cb730c6e9179353af3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1977</creationdate><topic>Circuits</topic><topic>Computational modeling</topic><topic>Encoding</topic><topic>Feedback</topic><topic>Latches</topic><topic>Logic arrays</topic><topic>Propagation delay</topic><topic>Sampling methods</topic><topic>System-on-a-chip</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Fryers, A.J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fryers, A.J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Fast Two-Bit Quantiser for Use in High Speed A to D Converter Systems</atitle><btitle>ESSCIRC '77: 3rd European Solid State Circuits Conference</btitle><stitle>ESSCIRC</stitle><date>1977-09</date><risdate>1977</risdate><spage>55</spage><epage>57</epage><pages>55-57</pages><isbn>9783800711321</isbn><isbn>380071132X</isbn><abstract>This paper describes a two-bit quantiser for use in A to D converters operating at sample rates up to 100 MHz. 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| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9783800711321 |
| ispartof | ESSCIRC '77: 3rd European Solid State Circuits Conference, 1977, p.55-57 |
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| language | eng |
| recordid | cdi_ieee_primary_5435064 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Computational modeling Encoding Feedback Latches Logic arrays Propagation delay Sampling methods System-on-a-chip Voltage |
| title | A Fast Two-Bit Quantiser for Use in High Speed A to D Converter Systems |
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