A memory efficient architecture of deblocking filter in H.264/AVC using hybrid processing order

In this paper, we propose a memory and performance optimized architecture to accelerate the operation speed of adaptive deblocking filter (DF) for H.264/JVT/AVC video coding. With the proposed processing order, we can reduce not only the number of internal buffer but also the size of the internal SR...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kyeong-Yuk Min, Jong-Wha Chong
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Acceleration Adaptive filters Automatic voltage control Bandwidth Clocks Deblocking filter Filtering Frequency H.264/AVC Memory architecture Random access memory SRAM throughput Video coding
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!