A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1996-11, Vol.31 (11), p.1635-1644, Article 1635
Hauptverfasser:	Yoo, Jei-Hwan, Kim, Chang-Hyun, Lee, Kyu-Chan, Kyung, Kye-Hyun, Yoo, Seung-Moon, Lee, Jung-Hwa, Son, Moon-Hae, Han, Jin-Man, Kang, Bok-Moon, Haq, Ejaz, Lee, Sang-Bo, Sim, Jai-Hoon, Kim, Joung-Ho, Moon, Byung-Sik, Kim, Keum-Yong, Park, Jae-Gwan, Lee, Kyu-Phil, Lee, Kang-Yoon, Kim, Ki-Nam
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth Circuits Clocks Delay Energy consumption Frequency Moon Multiprocessing systems Random access memory Registers
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