A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth
This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1996-11, Vol.31 (11), p.1635-1644, Article 1635 |
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| container_end_page | 1644 |
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| container_issue | 11 |
| container_start_page | 1635 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 31 |
| creator | Yoo, Jei-Hwan Kim, Chang-Hyun Lee, Kyu-Chan Kyung, Kye-Hyun Yoo, Seung-Moon Lee, Jung-Hwa Son, Moon-Hae Han, Jin-Man Kang, Bok-Moon Haq, Ejaz Lee, Sang-Bo Sim, Jai-Hoon Kim, Joung-Ho Moon, Byung-Sik Kim, Keum-Yong Park, Jae-Gwan Lee, Kyu-Phil Lee, Kang-Yoon Kim, Ki-Nam |
| description | This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology. |
| doi_str_mv | 10.1109/JSSC.1996.542308 |
| format | Article |
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The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.</description><subject>Bandwidth</subject><subject>Circuits</subject><subject>Clocks</subject><subject>Delay</subject><subject>Energy consumption</subject><subject>Frequency</subject><subject>Moon</subject><subject>Multiprocessing systems</subject><subject>Random access memory</subject><subject>Registers</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1996</creationdate><recordtype>article</recordtype><recordid>eNp9kDFPwzAQRi0EEqWwIyZPbGnPTpzYYym0gIqQKEhslp041JAmxXZV9d-TKBUDA9PpdN-7Oz2ELgmMCAExflwupyMiRDpiCY2BH6EBYYxHJIvfj9EAgPBIUIBTdOb9Z9smCScDNJvgmEZa1V-Y4LnG3lRl5INrtK0_sN_X-co1dbP1-PZl8oR3Nqy64M0-mLHHLVfsbBFW5-ikVJU3F4c6RG-zu9fpfbR4nj9MJ4sop4KEiBWJFplQDJRR3HDNCpIwlqpcG05BKYgJaF1SqtPSpECZKiARRoPIQJs8HqLrfu_GNd9b44NcW5-bqlK1aZ-UlJMsJalog9AHc9d470wpN86uldtLArITJjthshMme2Etkv5BchtUsE0dnLLVf-BVD1pjzO-dw_AHf3J2xg</recordid><startdate>19961101</startdate><enddate>19961101</enddate><creator>Yoo, Jei-Hwan</creator><creator>Kim, Chang-Hyun</creator><creator>Lee, Kyu-Chan</creator><creator>Kyung, Kye-Hyun</creator><creator>Yoo, Seung-Moon</creator><creator>Lee, Jung-Hwa</creator><creator>Son, Moon-Hae</creator><creator>Han, Jin-Man</creator><creator>Kang, Bok-Moon</creator><creator>Haq, Ejaz</creator><creator>Lee, Sang-Bo</creator><creator>Sim, Jai-Hoon</creator><creator>Kim, Joung-Ho</creator><creator>Moon, Byung-Sik</creator><creator>Kim, Keum-Yong</creator><creator>Park, Jae-Gwan</creator><creator>Lee, Kyu-Phil</creator><creator>Lee, Kang-Yoon</creator><creator>Kim, Ki-Nam</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19961101</creationdate><title>A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth</title><author>Yoo, Jei-Hwan ; Kim, Chang-Hyun ; Lee, Kyu-Chan ; Kyung, Kye-Hyun ; Yoo, Seung-Moon ; Lee, Jung-Hwa ; Son, Moon-Hae ; Han, Jin-Man ; Kang, Bok-Moon ; Haq, Ejaz ; Lee, Sang-Bo ; Sim, Jai-Hoon ; Kim, Joung-Ho ; Moon, Byung-Sik ; Kim, Keum-Yong ; Park, Jae-Gwan ; Lee, Kyu-Phil ; Lee, Kang-Yoon ; Kim, Ki-Nam</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-5d4b979a50aea8e8b5d14556acbe820aa0310bbf22b6fe6025ad049eb0970bec3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Bandwidth</topic><topic>Circuits</topic><topic>Clocks</topic><topic>Delay</topic><topic>Energy consumption</topic><topic>Frequency</topic><topic>Moon</topic><topic>Multiprocessing systems</topic><topic>Random access memory</topic><topic>Registers</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yoo, Jei-Hwan</creatorcontrib><creatorcontrib>Kim, Chang-Hyun</creatorcontrib><creatorcontrib>Lee, Kyu-Chan</creatorcontrib><creatorcontrib>Kyung, Kye-Hyun</creatorcontrib><creatorcontrib>Yoo, Seung-Moon</creatorcontrib><creatorcontrib>Lee, Jung-Hwa</creatorcontrib><creatorcontrib>Son, Moon-Hae</creatorcontrib><creatorcontrib>Han, Jin-Man</creatorcontrib><creatorcontrib>Kang, Bok-Moon</creatorcontrib><creatorcontrib>Haq, Ejaz</creatorcontrib><creatorcontrib>Lee, Sang-Bo</creatorcontrib><creatorcontrib>Sim, Jai-Hoon</creatorcontrib><creatorcontrib>Kim, Joung-Ho</creatorcontrib><creatorcontrib>Moon, Byung-Sik</creatorcontrib><creatorcontrib>Kim, Keum-Yong</creatorcontrib><creatorcontrib>Park, Jae-Gwan</creatorcontrib><creatorcontrib>Lee, Kyu-Phil</creatorcontrib><creatorcontrib>Lee, Kang-Yoon</creatorcontrib><creatorcontrib>Kim, Ki-Nam</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yoo, Jei-Hwan</au><au>Kim, Chang-Hyun</au><au>Lee, Kyu-Chan</au><au>Kyung, Kye-Hyun</au><au>Yoo, Seung-Moon</au><au>Lee, Jung-Hwa</au><au>Son, Moon-Hae</au><au>Han, Jin-Man</au><au>Kang, Bok-Moon</au><au>Haq, Ejaz</au><au>Lee, Sang-Bo</au><au>Sim, Jai-Hoon</au><au>Kim, Joung-Ho</au><au>Moon, Byung-Sik</au><au>Kim, Keum-Yong</au><au>Park, Jae-Gwan</au><au>Lee, Kyu-Phil</au><au>Lee, Kang-Yoon</au><au>Kim, Ki-Nam</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1996-11-01</date><risdate>1996</risdate><volume>31</volume><issue>11</issue><spage>1635</spage><epage>1644</epage><pages>1635-1644</pages><artnum>1635</artnum><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.</abstract><pub>IEEE</pub><doi>10.1109/JSSC.1996.542308</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1996-11, Vol.31 (11), p.1635-1644, Article 1635 |
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| language | eng |
| recordid | cdi_ieee_primary_542308 |
| source | IEEE Electronic Library (IEL) |
| subjects | Bandwidth Circuits Clocks Delay Energy consumption Frequency Moon Multiprocessing systems Random access memory Registers |
| title | A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth |
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