Secure and testable scan design using extended de Bruijn graphs
In this paper, we first introduce extended de Bruijn graphs to design extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. Using the extended shift registers, we present a new secure and testable scan design approach that aims to satisfy both...
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| creator | Fujiwara, H. Obien, M.E.J. |
| description | In this paper, we first introduce extended de Bruijn graphs to design extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. Using the extended shift registers, we present a new secure and testable scan design approach that aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan registers to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. New concepts of scan security and scan testability are also introduced. |
| doi_str_mv | 10.1109/ASPDAC.2010.5419845 |
| format | Conference Proceeding |
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Using the extended shift registers, we present a new secure and testable scan design approach that aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan registers to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. New concepts of scan security and scan testability are also introduced.</description><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Cryptography</subject><subject>Design for testability</subject><subject>Digital circuits</subject><subject>Flip-flops</subject><subject>Hardware</subject><subject>Information security</subject><subject>Shift registers</subject><subject>Switches</subject><issn>2153-6961</issn><issn>2153-697X</issn><isbn>9781424457656</isbn><isbn>1424457653</isbn><isbn>142445767X</isbn><isbn>9781424457670</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kNtKw0AYhNcTWGueoDf7Aqn7J3vIXklsPUFBoQq9K3v4E7fUpWQT0Lc3YHVuBuYb5mIImQGbAzB9U69fl_ViXrAxEBx0xcUJuQJecC6UVJtTMilAlLnUanNGMq2qPybk-T-TcEmylHZsFBdFIWBCbtfohg6piZ72mHpj90iTM5F6TKGNdEghthS_eowe_ZjSu24Iu0jbzhw-0jW5aMw-YXb0KXl_uH9bPOWrl8fnRb3KAwjZ58aCQG6akmnNLAOllDCWK-e4Y00pvVFeWmNAgau41cgYOmdLMbasLUQ5JbPf3YCI20MXPk33vT1-Uf4AdmFO-Q</recordid><startdate>201001</startdate><enddate>201001</enddate><creator>Fujiwara, H.</creator><creator>Obien, M.E.J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201001</creationdate><title>Secure and testable scan design using extended de Bruijn graphs</title><author>Fujiwara, H. ; Obien, M.E.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i156t-ab15e4af30990b017775ab47cc4c0f36da7d6baa171c84b9e00eccb355abbb253</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2010</creationdate><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Cryptography</topic><topic>Design for testability</topic><topic>Digital circuits</topic><topic>Flip-flops</topic><topic>Hardware</topic><topic>Information security</topic><topic>Shift registers</topic><topic>Switches</topic><toplevel>online_resources</toplevel><creatorcontrib>Fujiwara, H.</creatorcontrib><creatorcontrib>Obien, M.E.J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fujiwara, H.</au><au>Obien, M.E.J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Secure and testable scan design using extended de Bruijn graphs</atitle><btitle>2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)</btitle><stitle>ASPDAC</stitle><date>2010-01</date><risdate>2010</risdate><spage>413</spage><epage>418</epage><pages>413-418</pages><issn>2153-6961</issn><eissn>2153-697X</eissn><isbn>9781424457656</isbn><isbn>1424457653</isbn><eisbn>142445767X</eisbn><eisbn>9781424457670</eisbn><abstract>In this paper, we first introduce extended de Bruijn graphs to design extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. Using the extended shift registers, we present a new secure and testable scan design approach that aims to satisfy both testability and security of digital circuits. The approach is only to replace the original scan registers to modified scan registers called extended scan registers. This method requires very little area overhead and no performance overhead. New concepts of scan security and scan testability are also introduced.</abstract><pub>IEEE</pub><doi>10.1109/ASPDAC.2010.5419845</doi><tpages>6</tpages></addata></record> |
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| ispartof | 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, p.413-418 |
| issn | 2153-6961 2153-697X |
| language | eng ; jpn |
| recordid | cdi_ieee_primary_5419845 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit faults Circuit testing Cryptography Design for testability Digital circuits Flip-flops Hardware Information security Shift registers Switches |
| title | Secure and testable scan design using extended de Bruijn graphs |
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