Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs

Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs

Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an...

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Hauptverfasser: Shimeng Yu, Yuning Zhao, Yuncheng Song, Gang Du, Jinfeng Kang, Ruqi Han, Xiaoyan Liu
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Autocorrelation
FinFETs
Fluctuations
Leakage current
Microelectronics
MOSFETs
Random sequences
Root mean square
Solid modeling
Threshold voltage
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creator Shimeng Yu
Yuning Zhao
Yuncheng Song
Gang Du
Jinfeng Kang
Ruqi Han
Xiaoyan Liu
description Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an urgent issue when the channel length decreases into sub-30nm.
doi_str_mv 10.1109/SNW.2008.5418481
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5418481</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5418481</ieee_id><sourcerecordid>5418481</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-50a18dfbe8736c3e38f589e68558586932256a449f0fec418d75240609d3a7cf3</originalsourceid><addsrcrecordid>eNo9UMtKw0AUHdSCtXYvuJkfSL13XplZSjU-KLqw4LJMkztxJElLJ1n4941YXB04LziHsRuEBSK4u4-3z4UAsAut0CqLZ2wq0GCmjFLnbO5yi0ooJSBHvPjXpJmwq9-YA5DaXLJ5St8AgM7kCGbKXouhabjMHniK7dD4Pu46vgu89j3xJnbEqaqJH3ZD_dVRSjy2e1_2fHSlYZtJ6FpexK54XKdrNgm-STQ_4YytR3r5nK3en16W96ssOugzDR5tFbZkc2lKSdIGbR0Zq7XV1jgphDZeKRcgUDlurXItFBhwlfR5GeSM3f7VRiLa7A-x9YefzekVeQSpCk6x</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Shimeng Yu ; Yuning Zhao ; Yuncheng Song ; Gang Du ; Jinfeng Kang ; Ruqi Han ; Xiaoyan Liu</creator><creatorcontrib>Shimeng Yu ; Yuning Zhao ; Yuncheng Song ; Gang Du ; Jinfeng Kang ; Ruqi Han ; Xiaoyan Liu</creatorcontrib><description>Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an urgent issue when the channel length decreases into sub-30nm.</description><identifier>ISSN: 2161-4636</identifier><identifier>ISBN: 9781424420711</identifier><identifier>ISBN: 1424420717</identifier><identifier>EISSN: 2161-4644</identifier><identifier>DOI: 10.1109/SNW.2008.5418481</identifier><identifier>LCCN: 2008900356</identifier><language>eng</language><publisher>IEEE</publisher><subject>Autocorrelation ; FinFETs ; Fluctuations ; Leakage current ; Microelectronics ; MOSFETs ; Random sequences ; Root mean square ; Solid modeling ; Threshold voltage</subject><ispartof>2008 IEEE Silicon Nanoelectronics Workshop, 2008, p.1-2</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5418481$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5418481$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Shimeng Yu</creatorcontrib><creatorcontrib>Yuning Zhao</creatorcontrib><creatorcontrib>Yuncheng Song</creatorcontrib><creatorcontrib>Gang Du</creatorcontrib><creatorcontrib>Jinfeng Kang</creatorcontrib><creatorcontrib>Ruqi Han</creatorcontrib><creatorcontrib>Xiaoyan Liu</creatorcontrib><title>Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs</title><title>2008 IEEE Silicon Nanoelectronics Workshop</title><addtitle>SNW</addtitle><description>Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an urgent issue when the channel length decreases into sub-30nm.</description><subject>Autocorrelation</subject><subject>FinFETs</subject><subject>Fluctuations</subject><subject>Leakage current</subject><subject>Microelectronics</subject><subject>MOSFETs</subject><subject>Random sequences</subject><subject>Root mean square</subject><subject>Solid modeling</subject><subject>Threshold voltage</subject><issn>2161-4636</issn><issn>2161-4644</issn><isbn>9781424420711</isbn><isbn>1424420717</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9UMtKw0AUHdSCtXYvuJkfSL13XplZSjU-KLqw4LJMkztxJElLJ1n4941YXB04LziHsRuEBSK4u4-3z4UAsAut0CqLZ2wq0GCmjFLnbO5yi0ooJSBHvPjXpJmwq9-YA5DaXLJ5St8AgM7kCGbKXouhabjMHniK7dD4Pu46vgu89j3xJnbEqaqJH3ZD_dVRSjy2e1_2fHSlYZtJ6FpexK54XKdrNgm-STQ_4YytR3r5nK3en16W96ssOugzDR5tFbZkc2lKSdIGbR0Zq7XV1jgphDZeKRcgUDlurXItFBhwlfR5GeSM3f7VRiLa7A-x9YefzekVeQSpCk6x</recordid><startdate>200806</startdate><enddate>200806</enddate><creator>Shimeng Yu</creator><creator>Yuning Zhao</creator><creator>Yuncheng Song</creator><creator>Gang Du</creator><creator>Jinfeng Kang</creator><creator>Ruqi Han</creator><creator>Xiaoyan Liu</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200806</creationdate><title>Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs</title><author>Shimeng Yu ; Yuning Zhao ; Yuncheng Song ; Gang Du ; Jinfeng Kang ; Ruqi Han ; Xiaoyan Liu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-50a18dfbe8736c3e38f589e68558586932256a449f0fec418d75240609d3a7cf3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Autocorrelation</topic><topic>FinFETs</topic><topic>Fluctuations</topic><topic>Leakage current</topic><topic>Microelectronics</topic><topic>MOSFETs</topic><topic>Random sequences</topic><topic>Root mean square</topic><topic>Solid modeling</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Shimeng Yu</creatorcontrib><creatorcontrib>Yuning Zhao</creatorcontrib><creatorcontrib>Yuncheng Song</creatorcontrib><creatorcontrib>Gang Du</creatorcontrib><creatorcontrib>Jinfeng Kang</creatorcontrib><creatorcontrib>Ruqi Han</creatorcontrib><creatorcontrib>Xiaoyan Liu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shimeng Yu</au><au>Yuning Zhao</au><au>Yuncheng Song</au><au>Gang Du</au><au>Jinfeng Kang</au><au>Ruqi Han</au><au>Xiaoyan Liu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs</atitle><btitle>2008 IEEE Silicon Nanoelectronics Workshop</btitle><stitle>SNW</stitle><date>2008-06</date><risdate>2008</risdate><spage>1</spage><epage>2</epage><pages>1-2</pages><issn>2161-4636</issn><eissn>2161-4644</eissn><isbn>9781424420711</isbn><isbn>1424420717</isbn><abstract>Summary form only given. Through full 3D simulation, we evaluate the impact of gate LER mainly focuses on device parameters including SS, DIBL and Ioff. The variation of the device performance increases when rms amplitude or correlation length increases. Also our results show that gate LER become an urgent issue when the channel length decreases into sub-30nm.</abstract><pub>IEEE</pub><doi>10.1109/SNW.2008.5418481</doi><tpages>2</tpages></addata></record>
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Autocorrelation
FinFETs
Fluctuations
Leakage current
Microelectronics
MOSFETs
Random sequences
Root mean square
Solid modeling
Threshold voltage
title Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T20%3A13%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Full%203-D%20simulation%20of%20gate%20line%20edge%20roughness%20impact%20on%20sub-30nm%20FinFETs&rft.btitle=2008%20IEEE%20Silicon%20Nanoelectronics%20Workshop&rft.au=Shimeng%20Yu&rft.date=2008-06&rft.spage=1&rft.epage=2&rft.pages=1-2&rft.issn=2161-4636&rft.eissn=2161-4644&rft.isbn=9781424420711&rft.isbn_list=1424420717&rft_id=info:doi/10.1109/SNW.2008.5418481&rft_dat=%3Cieee_6IE%3E5418481%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5418481&rfr_iscdi=true