Reincarnate historic systems on FPGA with novel design methodology
In this paper, I introduce my and my students projects to reincarnate historic systems on FPGA. Our projects are not replica nor paper-model of historic systems, but reorganized and working system on FPGA with novel and progressive design methodology. I mean progressive as under the development, bec...
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| description | In this paper, I introduce my and my students projects to reincarnate historic systems on FPGA. Our projects are not replica nor paper-model of historic systems, but reorganized and working system on FPGA with novel and progressive design methodology. I mean progressive as under the development, because I have developed them and I am still improving the methodology and tools very often to use them by myself. In this paper, I also introduce my design methodology and tools which is used in my and my students projects. |
| doi_str_mv | 10.1109/ICCD.2009.5413182 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5413182</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5413182</ieee_id><sourcerecordid>5413182</sourcerecordid><originalsourceid>FETCH-LOGICAL-i218t-31f40fdea8ce41bc16c984a62d786b81b704f8c560bd5d29a063ee03489467133</originalsourceid><addsrcrecordid>eNpFkM1KAzEUheMfONY-gLjJC0zNTW4yybJObS0UFNF1yczcaSPzI5NB6dtbsODZnMUHh4_D2B2IGYBwD-s8X8ykEG6mERRYecZuACWiFtLiOUukzkxqnDMX_8DJS5aAMCo1KPCaTWP8FMegVqB0wh7fKHSlHzo_Et-HOPZDKHk8xJHayPuOL19Xc_4Txj3v-m9qeEUx7Dre0rjvq77pd4dbdlX7JtL01BP2sXx6z5_Tzctqnc83aZBgx1RBjaKuyNuSEIoSTOkseiOrzJrCQpEJrG2pjSgqXUnnj9JEQqF1aDJQasLu_3YDEW2_htD64bA9faF-AeVcTbQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Reincarnate historic systems on FPGA with novel design methodology</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Shimizu, N.</creator><creatorcontrib>Shimizu, N.</creatorcontrib><description>In this paper, I introduce my and my students projects to reincarnate historic systems on FPGA. Our projects are not replica nor paper-model of historic systems, but reorganized and working system on FPGA with novel and progressive design methodology. I mean progressive as under the development, because I have developed them and I am still improving the methodology and tools very often to use them by myself. In this paper, I also introduce my design methodology and tools which is used in my and my students projects.</description><identifier>ISSN: 1063-6404</identifier><identifier>ISBN: 1424450292</identifier><identifier>ISBN: 9781424450299</identifier><identifier>EISSN: 2576-6996</identifier><identifier>EISBN: 1424450284</identifier><identifier>EISBN: 9781424450282</identifier><identifier>DOI: 10.1109/ICCD.2009.5413182</identifier><language>eng</language><publisher>IEEE</publisher><subject>Central Processing Unit ; Design engineering ; Design methodology ; Electronic design automation and methodology ; Field programmable gate arrays ; Hardware design languages ; Laboratories ; Unified modeling language</subject><ispartof>2009 IEEE International Conference on Computer Design, 2009, p.10-15</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5413182$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5413182$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Shimizu, N.</creatorcontrib><title>Reincarnate historic systems on FPGA with novel design methodology</title><title>2009 IEEE International Conference on Computer Design</title><addtitle>ICCD</addtitle><description>In this paper, I introduce my and my students projects to reincarnate historic systems on FPGA. Our projects are not replica nor paper-model of historic systems, but reorganized and working system on FPGA with novel and progressive design methodology. I mean progressive as under the development, because I have developed them and I am still improving the methodology and tools very often to use them by myself. In this paper, I also introduce my design methodology and tools which is used in my and my students projects.</description><subject>Central Processing Unit</subject><subject>Design engineering</subject><subject>Design methodology</subject><subject>Electronic design automation and methodology</subject><subject>Field programmable gate arrays</subject><subject>Hardware design languages</subject><subject>Laboratories</subject><subject>Unified modeling language</subject><issn>1063-6404</issn><issn>2576-6996</issn><isbn>1424450292</isbn><isbn>9781424450299</isbn><isbn>1424450284</isbn><isbn>9781424450282</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkM1KAzEUheMfONY-gLjJC0zNTW4yybJObS0UFNF1yczcaSPzI5NB6dtbsODZnMUHh4_D2B2IGYBwD-s8X8ykEG6mERRYecZuACWiFtLiOUukzkxqnDMX_8DJS5aAMCo1KPCaTWP8FMegVqB0wh7fKHSlHzo_Et-HOPZDKHk8xJHayPuOL19Xc_4Txj3v-m9qeEUx7Dre0rjvq77pd4dbdlX7JtL01BP2sXx6z5_Tzctqnc83aZBgx1RBjaKuyNuSEIoSTOkseiOrzJrCQpEJrG2pjSgqXUnnj9JEQqF1aDJQasLu_3YDEW2_htD64bA9faF-AeVcTbQ</recordid><startdate>20090101</startdate><enddate>20090101</enddate><creator>Shimizu, N.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20090101</creationdate><title>Reincarnate historic systems on FPGA with novel design methodology</title><author>Shimizu, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i218t-31f40fdea8ce41bc16c984a62d786b81b704f8c560bd5d29a063ee03489467133</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Central Processing Unit</topic><topic>Design engineering</topic><topic>Design methodology</topic><topic>Electronic design automation and methodology</topic><topic>Field programmable gate arrays</topic><topic>Hardware design languages</topic><topic>Laboratories</topic><topic>Unified modeling language</topic><toplevel>online_resources</toplevel><creatorcontrib>Shimizu, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shimizu, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Reincarnate historic systems on FPGA with novel design methodology</atitle><btitle>2009 IEEE International Conference on Computer Design</btitle><stitle>ICCD</stitle><date>2009-01-01</date><risdate>2009</risdate><spage>10</spage><epage>15</epage><pages>10-15</pages><issn>1063-6404</issn><eissn>2576-6996</eissn><isbn>1424450292</isbn><isbn>9781424450299</isbn><eisbn>1424450284</eisbn><eisbn>9781424450282</eisbn><abstract>In this paper, I introduce my and my students projects to reincarnate historic systems on FPGA. Our projects are not replica nor paper-model of historic systems, but reorganized and working system on FPGA with novel and progressive design methodology. I mean progressive as under the development, because I have developed them and I am still improving the methodology and tools very often to use them by myself. In this paper, I also introduce my design methodology and tools which is used in my and my students projects.</abstract><pub>IEEE</pub><doi>10.1109/ICCD.2009.5413182</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
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| identifier | ISSN: 1063-6404 |
| ispartof | 2009 IEEE International Conference on Computer Design, 2009, p.10-15 |
| issn | 1063-6404 2576-6996 |
| language | eng |
| recordid | cdi_ieee_primary_5413182 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Central Processing Unit Design engineering Design methodology Electronic design automation and methodology Field programmable gate arrays Hardware design languages Laboratories Unified modeling language |
| title | Reincarnate historic systems on FPGA with novel design methodology |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T03%3A01%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Reincarnate%20historic%20systems%20on%20FPGA%20with%20novel%20design%20methodology&rft.btitle=2009%20IEEE%20International%20Conference%20on%20Computer%20Design&rft.au=Shimizu,%20N.&rft.date=2009-01-01&rft.spage=10&rft.epage=15&rft.pages=10-15&rft.issn=1063-6404&rft.eissn=2576-6996&rft.isbn=1424450292&rft.isbn_list=9781424450299&rft_id=info:doi/10.1109/ICCD.2009.5413182&rft_dat=%3Cieee_6IE%3E5413182%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424450284&rft.eisbn_list=9781424450282&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5413182&rfr_iscdi=true |